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| preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. september 2009 doc id 15962 rev 2 1/101 1 stm8l151xx, stm8l152xx 8-bit ultralow power mcu, up to 32 kb flash, 1 kb data eeprom rtc, lcd, timers, usart, i2c, spi, adc, dac, comparators features operating conditions ? operating power supply range 1.8 v to 3.6 v (down to 1.65 v at power down) ? temperature range: - 40 c to 85 or 125 c low power features ? 5 low power modes: wait , low power run (5.4 a), low power wait (3 a), active-halt with rtc (1 a), halt (400 na) ? dynamic consumption: 192 a/mhz ? ultralow leakage per i/0: 50 na ? fast wakeup from halt: 5 s advanced stm8 core ? harvard architecture and 3-stage pipeline ? max freq. 16 mhz, 16 cisc mips peak ? up to 40 external interrupt sources reset and supply management ? low power, ultrasafe bor reset with 5 selectable thresholds ? ultralow power por/pdr ? programmable voltage detector (pvd) clock management ? 1 to 16 mhz crystal oscillator ? 32 khz crystal oscillator ? internal 16 mhz factory-trimmed rc ? internal 38 khz low consumption rc ? clock security system low power rtc ? bcd calendar with alarm interrupt ? auto-wakeup from halt w/ periodic interrupt lcd: up to 4x28 segments w/ step-up converter memories ? up to 32 kb of flash program memory and 1 kbyte of data eeprom with ecc, rww ? flexible write and read protection modes ? up to 2 kbytes of ram dma ? 4 channels; supported peripherals: adc, dac, spi, i2c, usart, timers ? 1 channel for memory-to-memory 12-bit dac with output buffer 12-bit adc up to 1 msps/25 channels ? t. sensor and internal reference voltage 2 ultralow power comparators ? 1 with fixed threshold and 1 rail to rail ? wakeup capability timers ? two 16-bit timers with 2 channels (used as ic, oc, pwm), quadrature encoder ? one 16-bit advanced control timer with 3 channels, supporting motor control ? one 8-bit timer with 7-bit prescaler ? 2 watchdogs: 1 window, 1 independent ? beeper timer with 1, 2 or 4 khz frequencies communication interfaces ? synchronous serial interface (spi) ? fast i2c 400 khz smbus and pmbus ? usart (iso 7816 interface and irda) up to 41 i/os, all mappab le on interrupt vectors up to 16 capacitive sensing channels with free firmware development support ? fast on-chip programming and non intrusive debugging with swim ? bootloader using usart 96-bit unique id table 1. device summary reference part number stm8l151xx (without lcd) stm8l151c6, stm8l151c4, stm8l151k6, stm8l151k4, stm8l151g6, stm8l151g4 stm8l152xx (with lcd) stm8l152c6, stm8l152c4, stm8l152k6, stm8l152k4 vfqfpn48 lqfp32 wfqfpn28 wfqfpn32 lqfp48 www.st.com
contents stm8l151xx, stm8l152xx 2/101 doc id 15962 rev 2 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 ultralow power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 advanced stm8 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.2 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 lcd (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 ultralow power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 system configuration controller and routi ng interface . . . . . . . . . . . . . . . 19 3.13 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13.1 tim1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.2 independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 stm8l151xx, stm8l152xx contents doc id 15962 rev 2 3/101 3.16 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.16.1 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.16.2 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.16.3 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.17 infrared (ir) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.18 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 system configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3.2 power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 59 8.3.3 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.3.4 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.3.7 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3.8 lcd controller (stm8l152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3.9 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.3.10 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 contents stm8l151xx, stm8l152xx 4/101 doc id 15962 rev 2 8.3.11 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.3.12 12-bit dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.3.13 12-bit adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3.14 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.1 ecopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 stm8l151xx, stm8l152xx list of tables doc id 15962 rev 2 5/101 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm8l15x low power device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 10 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. stm8l15x pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5. flash and ram boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 9. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 10. option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 11. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 12. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 13. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 14. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 15. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 16. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 17. total current consumption in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 18. total current consumption in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 19. total current consumption and timing in low power run mode at vdd = 1.65 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 20. total current consumption in low power wait mode at vdd = 1.65 v to 3.6 v . . . . . . . . . 65 table 21. total current consumption and timing in active-halt mode at vdd = 1.65 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 22. total current consumption and timing in halt mode at vdd = 2 v . . . . . . . . . . . . . . . . . . 67 table 23. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 24. hse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 25. lse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 26. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 27. lse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 28. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 29. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 30. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 31. flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 32. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 33. output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 34. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 35. output driving current (pa0 wi th high sink led driver capability). . . . . . . . . . . . . . . . . . . . 75 table 36. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 37. spi1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 38. i2c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 39. lcd characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 40. reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 41. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 42. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 43. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 44. dac characteristics, output on pf0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 45. dac output on pb4-pb5-pb6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 46. adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 list of tables stm8l151xx, stm8l152xx 6/101 doc id 15962 rev 2 table 47. adc1 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 48. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 49. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 50. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 51. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 52. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 53. wfqfpn28 ? 28-lead very very thin fine pitch quad flat no-lead package (4 x 4), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 54. wfqfpn32 ? 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 55. lqfp32 ? 32-pin low profile quad flat package, package mechanical data . . . . . . . . . . . . 96 table 56. vfqfpn48 ? very thin fine pitch quad flat pack no-lead 7 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 57. lqfp48 ? 48-pin low profile quad flat package (7x7), package mechanical data . . . . . . . 98 stm8l151xx, stm8l152xx list of figures doc id 15962 rev 2 7/101 list of figures figure 1. stm8l15xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. stm8l15x clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. stm8l151gx 28-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. stm8l151kx 32-pin package pinout (without lcd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5. stm8l152kx 32-pin package pinout (with lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. stm8l151cx 48-pin pinout (without lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. stm8l152cx 48-pin pinout (with lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 11. por/bor thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 12. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 13. lse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 14. recommended nrst pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 15. spi timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 16. spi timing diagram - slave mode and cpha=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 17. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 18. typical application with i2c bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 19. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 88 figure 20. power supply and reference decoupling (vref+ connected to vdda) . . . . . . . . . . . . . . . 89 figure 21. wfqfpn28 ? 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) . 94 figure 22. recommended footprint (dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 23. wfqfpn32 ? 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 24. lqfp32 ? 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 25. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 26. recommended footprint (dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 27. lqfp48 ? 48-pin low profile quad flat package outline (7x7) . . . . . . . . . . . . . . . . . . . . . . . 98 figure 28. stm8l15xxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 introduction stm8l151xx, stm8l152xx 8/101 doc id 15962 rev 2 1 introduction this document describes the stm8l15xxx family features, pinout, mechanical data and ordering information. for more details on the whole stmicroelectro nics ultralow power family please refer to section 2.2: ultralow power continuum on page 11 . the reference manual and flash progra mming manuals will be available soon. for information on the debug module and swim (single wire interface module), refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044). 2 description the stm8l15xxx devices are members of the stm8l ultralow power 8-bit family. they are referred to as medium -density devices in the stm8l15 xxx reference manual (rm0031) and in the stm8l flash programming manual (pm0054). they provide the following benefits: integrated system ? up to 32 kbytes of medium-density embedded flash program memory ? 1 kbyte of data eeprom ? internal high speed and low-power low speed rc. ? embedded reset ultralow power consumption ? 192 a/mhz (dynamic consumption) ? 1 a in active-halt mode ? clock gated system and optimized power management ? capability to execute from ram for lo w power wait mode and low power run mode advanced features ? up to 16 mips at 16 mhz cpu clock frequency ? direct memory access (dma) for memory-to-memory or peripheral-to-memory access. short development cycles ? application scalability acro ss a common family prod uct architecture with compatible pinout, memory map and modular peripherals. ? wide choice of development tools the stm8l15xxx family operates from 1.8 v to 3.6 v (down to 1.65 v at power down) and is available in the - 40 to +85 c and - 40 to +125 c temperature ranges. the stm8l15xxx ultralow power family features the enhanced stm8 cpu core providing increased processing power (up to 16 mips at 16 mhz) while maintaining the advantages of stm8l151xx, stm8l152xx description doc id 15962 rev 2 9/101 a cisc architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. the family includes an integrated debug module with a hardware interface (swim) which allows non-intrusive in-application deb ugging and ultrafast flash programming. all stm8l15xxx microcontrollers featur e embedded data eeprom and low power low- voltage single-supply program flash memory. the stm8l15xxx family 8-bit microcontrollers incorporate an extensive range of enhanced i/os and peripherals. all devices offer 12-bit adc, dac, two comparators, real-time clock three 16-bit timers, one 8-bit timer as well as standard communication interface such as spi, i2c and usart. a 4x28-segment lcd is available on the stm8l152xx line. the modular design of the peripheral set allows the same peripherals to be found in different st microcontroller families includ ing 32-bit families. this make s any transition to a different family very easy, and simplified even more by the use of a common set of development tools. these features make the stm8l15xxx microcontroller family suitable for a wide range of applications: medical and handheld equipment application control and user interface pc peripherals, gaming, gps and sport equipment alarm systems, wired and wireless sensors figure 1 on page 12 shows the general block diagram of the device family. six different packages are proposed from 28 to 48 pins. depending on the device chosen, different sets of peripherals are included. section 3 on page 12 gives an overview of the complete range of peripherals proposed in this family. all stm8l ultralow power products are based on the same architecture with the same memory mapping and a coherent pinout. description stm8l151xx, stm8l152xx 10/101 doc id 15962 rev 2 2.1 device overview table 2. stm8l15x low power device features and peripheral counts features stm8l151gx stm8l15xkx stm8l15xcx flash (kbytes) 16 32 16 32 16 32 data eeprom (kbytes) 1 ram-kbytes 2 2 2 lcd no 4x17 (1) 4x28 (1) timers basic 1 (8-bit) 1 (8-bit) 1 (8-bit) general purpose 2 (16-bit) 2 (16-bit) 2 (16-bit) advanced control 1 (16-bit) 1 (16-bit) 1 (16-bit) communication interfaces spi 1 1 1 i2c 1 1 1 usart 1 1 1 gpios 26 (3) 30 (2)(3) or 29 (1)(3) 41 (3) 12-bit synchronized adc (number of channels) 1 (18) 1 (22 (2) or 21 (1) ) 1 (25) 12-bit dac (number of channels) 1 (1) 1 (1) 1 (1) comparators comp1/comp2 2 2 2 others rtc, window watchdog, independent watchdog, 16-mhz and 38-khz internal rc, 1- to 16-mhz and 32-khz external oscillator cpu frequency 16 mhz operating voltage 1.8 v to 3.6 v (down to 1.65 v at power down) operating temperature -40 to +85 c / -40 to +125 c packages wfqfpn28 (4) (4x4; 0.8 mm thickness) wfqfpn32 (5) (5x5; 0.8 mm thickness) lqfp32(7x7) vfqfpn48 (6) (4x4; 1 mm thickness) lqfp48 1. stm8l152xx versions only 2. stm8l151xx versions only 3. the number of gpios given in this table includes the nrs t/pa1 pin but the application can use the nrst/pa1 pin as general purpose output only (pa1). 4. wfqfpn28 package used in the sampling phase. in the pr oduction phase, the ufqfpn28 package will be used with a thickness equal to 0.6 mm. 5. wfqfpn32 package used in the sampling phase. in the pr oduction phase, the ufqfpn32 package will be used with a thickness equal to 0.6 mm. 6. vfqfpn48 package used in the sampling phase. in the production phase, the ufqfpn48 package will be used with a thickness equal to 0.6 mm. stm8l151xx, stm8l152xx description doc id 15962 rev 2 11/101 2.2 ultralow power continuum the ultralow power stm8l151xx and stm8l152xx are fully pin-to-pin, software and feature compatible. besides the full compatibility wit hin the family, the devices are part of stmicroelectronics microcontrollers utr alowpower strategy which also includes stm8l101xx and stm32 l15xxx. the stm8l and stm32l families allow a continuum of performance, peripherals, system architecture, and features. they are all based on stmicroelectronics 0.13 m ultralow leakage process. note: 1 the stm8l151xx and stm8l152xx are pin-to-pin compatible with stm8l101xx devices. 2 the stm32l family is pin-to-pin compatible with the general purpose stm32f family. please refer to stm32l15x documentation for more information on these devices. performance all families incorporate highly energy-efficien t cores with both harvar d architecture and pipelined execution: advanced stm8 core fo r stm8l families and arm cortex?-m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultralow power performance to range from 5 up to 33.3 dmips. shared peripherals stm8l151xx/152xx and stm32l15xx share identical peripherals which ensure a very easy migration from one family to another: analog peripherals: adc1, dac, and comparators comp1/comp2 digital peripherals: rtc and some communication interfaces common system strategy to offer flexibility and opti mize performance, the stm8 l151xx/152xx and stm32l15xx devices use a common architecture: same power supply range from 1.8 to 3.6 v, down to 1.65 v at power down architecture optimized to reach ultralow consumption both in low power modes and run mode fast startup strategy from low power modes flexible system clock ultrasafe reset: same reset strategy for both stm8l15xxx and stm32l15xxx including power-on reset, power-down reset, brownout reset and programmable voltage detector. features st utralowpower continuum also lies in feature compatibility: more than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm memory density ranging from 4 to 128 kbytes functional overview stm8l151xx, stm8l152xx 12/101 doc id 15962 rev 2 3 functional overview figure 1. stm8l15xxx device block diagram 1. legend : adc: analog-to-digital converter bor: brownout reset dma: direct memory access dac: digital-to-analog converter i2c: inter-integrated circuit multimaster interface iwdg: independent watchdog lcd: liquid crystal display por/pdr: power on reset / power down reset rtc: real-time clock spi: serial peripheral interface swim: single wire interface module usart: universal synchronous asyn chronous receiver transmitter wwdg: window watchdog 16 mhz internal rc clock clocks address, control and data buses debug module spi1 32 kbytes interrupt controller 2 kbytes ram to core and peripherals iwdg (38 khz clock) (swim) port a port b port c i2c1 usart1 power volt. reg. port f 1-16 mhz oscillator 32 khz oscillator 38 khz internal rc lcd driver 4x28 wwdg stm8 core controller and css 1 kbyte port d port e beeper rtc memory program data eeprom @v dd v dd18 v dd =1.65 v v ss swim scl, sda, mosi, miso, sck, nss rx, tx, ck adc1_inx dac_out comp1_inp comp 1 comp 2 comp2_inp v dda v ssa smb @v dda /v ssa temp sensor 12-bit adc1 v ddref v ssref 3.6 v 12-bit dac 12-bit dac nrst pa[7:0] pb[7:0] pc[7:0] pd[7:0] pe[7:0] pf0 beep alarm, calib segx, comx por/pdr osc_in, osc_out osc32_in, osc32_out to bor pvd pvd_in reset dma1 8-bit timer 4 16-bit timer 3 16-bit timer 2 16-bit timer 1 (4 channels) 2 channels 2 channels 3 channels comp2_inm v lcd = 2.5 v 3.6 v to lcd booster internal reference voltage vrefint out v ddref v ssref infrared interface ir_tim stm8l151xx, stm8l152xx functional overview doc id 15962 rev 2 13/101 3.1 low power modes the stm8l15xxx supports five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: wait mode : cpu clock is stopped, but selected peripherals keep running. an internal or external interrupt or a reset can be used to exit the microcontroller from wait mode (wfe or wfi mode). wait consumption is around 350 a. low power run mode : cpu clock runs. flash, data eeprom, voltage regulator and all peripherals are stopped except rtc and one other peripheral which can remain active (ex: one timer). execution is done fr om ram with a low speed oscillator (lsi or lse). the microcontroller enters low power run mode by software and can exit from this mode by software or by a reset. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. low power run mode consumption is around 5.4 a (peripherals off). low power wait mode: this mode is entered when executing a wait for event in low power run mode. it is similar to low power run mode except that the cpu clock is stopped. the wakeup from this mode is triggered by a reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, dma controller (dma1), comparators and i/o ports). when the wakeup is triggered by an event, the system goes back to low power run mode. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. low power wait mode consumption is around 3 a (peripherals off). active-halt mode : cpu and peripheral clocks are stopped, except rtc. the wakeup can be triggered by rtc interrupts, external interrupts or reset. active-halt consumption with rtc on lsi is 0.9 a. ac tive-halt consumption with rtc on lse is 1 a. halt mode : cpu and peripheral clocks are stopped, the device remains powered on. the wakeup is triggered by an external interrupt or reset. a few peripherals have also a wakeup from halt capability. switching off th e internal reference voltage reduces power consumption. through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 6 s. halt consumption is 400 na. dynamic consumption in run mode is 190 a/mhz. 3.2 central processing unit stm8 3.2.1 advanced stm8 core the 8-bit stm8 core is designed for code efficiency and performance with an harvard architecture and a 3-stage pipeline. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus - si ngle cycle fetching most instructions x and y 16-bit index registers - enabling indexed addressing modes with or without functional overview stm8l151xx, stm8l152xx 14/101 doc id 15962 rev 2 offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16 mbyte linear memory space 16-bit stack pointer - access to a 64 kbyte level stack 8-bit condition code register - 7 condition flags for the result of the last instruction addressing 20 addressing modes indexed indirect addressing mode for lookup tables located anywhere in the address space stack pointer relative addressing mode for local variables and parameter passing instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers 3.2.2 interrupt controller the stm8l15xxx features a nested vectored interrupt controller: nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority up to 40 external interrupt sources on 11 vectors trap and reset interrupts stm8l151xx, stm8l152xx functional overview doc id 15962 rev 2 15/101 3.3 reset and supply management 3.3.1 power supply scheme the device requires a 1.65 v to 3.6 v operating supply voltage (v dd ). the external power supply pins must be connected as follows: v ss ; v dd = 1.8 to 3.6 v, down to 1.65 v at power down: external power supply for i/os and for the internal regulator. provided externally through v dd pins, the corresponding ground pin is v ss . v ssa ; v dda = 1.8 to 3.6 v, down to 1.65 v at power down: external power supplies for analog peripherals (minimum voltage to be applied to v dda is 1.8 v when the adc1 is used). v dda and v ssa must be connected to v dd and v ss , respectively. v ssio ; v ddio = 1.8 to 3.6 v, down to 1.65 v at power down: external power supplies for i/os. v ddio and v ssio must be connected to v dd and v ss , respectively. v ref+ ; v ref- (for adc1): external reference voltage for adc1. must be provided externally through v ref+ and v ref- pin. v ref+ (for dac): external voltage reference for dac must be provided externally through v ref+ . 3.3.2 power supply supervisor the device has an integrated zeropower power-on reset (por)/power-down reset (pdr), coupled with a brownout reset (bor) circuitry. at power-on, bor is always active, and ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently (in which case, the v dd min value at power down is 1.65 v). five bor thresholds are available through option bytes, starting from 1.8 v to 3 v. to reduce the power consumption in halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the bor) in halt mode. the device remains in reset state when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.3.3 voltage regulator the stm8l15xxx embeds an internal voltage regulator for generating the 1.8 v power supply for the core and peripherals. this regulator has two different modes: main voltage regulator mode (mv r) for run, wait for interrupt (wfi) and wait for event (wfe) modes. low power voltage regulator mode (lpvr) for halt, active-halt, low power run and low power wait modes. functional overview stm8l151xx, stm8l152xx 16/101 doc id 15962 rev 2 when entering halt or active-halt modes, the system automatically switches from the mvr to the lpvr in order to reduce current consumption. 3.4 clock management the clock controller distributes the system clock (sysclk) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. system clock sources: 4 different clock sources can be used to drive the system clock: ? 1-16 mhz high speed external crystal (hse) ? 16 mhz high speed internal rc oscillator (hsi) ? 32.768 low speed external crystal (lse) ? 38 khz low speed internal rc (lsi) rtc and lcd clock sources: the above four sources can be chosen to clock the rtc and the lcd, whatever the system clock. startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the system clock is automatically switched to hsi. configurable main clock output (cco): this outputs an external clock for use by the application. stm8l151xx, stm8l152xx functional overview doc id 15962 rev 2 17/101 figure 2. stm8l15x clock tree diagram 3.5 low power real-time clock the real-time clock (rtc) is an independent binary coded decimal (bcd) timer/counter. six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in bcd (binary coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day months are made automatically. it provides a programmable alarm and programmable periodic interrupts with wakeup from halt capability. periodic wakeup time using the 32.768 khz lse with the lowest resolution (of 61 s) is from min. 122 s to max. 3.9 s. with a different resolution, the wakeup time can reach 36 hours periodic alarms based on the calendar can also be generated from every second to every year active-halt consumption with lsi and auto-wakeup: 0.9 a active-halt consumption with lse, calendar and auto-wakeup: 1 a ( 3 % / 3 # - ( z ( 3 ) 2 # - ( z , 3 ) 2 # k ( z , 3 % / 3 # k ( z ( 3 ) , 3 ) 2 4 # p r e s c a l e r 0 # , + t o p e r i p h e r a l s 2 4 # # , + t o , # $ t o ) 7 $ ' 3 9 3 # , + ( 3 % , 3 ) , 3 % / 3 # ? / 5 4 / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? ) . c l o c k o u t p u t # # / p r e s c a l e r ( 3 ) , 3 ) ( 3 % , 3 % # # / t o c o r e a n d m e m o r y 3 9 3 # , + 0 r e s c a l e r ) 7 $ ' # , + 2 4 # 3 % , ; = , 3 % # , + " % % 0 3 % , ; = t o " % % 0 " % % 0 # , + a i d # 3 3 c o n f i g u r a b l e 0 e r i p h e r a l # l o c k e n a b l e b i t s t o 2 4 # 2 4 # # , + c l o c k e n a b l e b i t , # $ # , + t o , # $ 3 9 3 # , + ( a l t c l o c k e n a b l e b i t , # $ p e r i p h e r a l 2 4 # # , + , # $ p e r i p h e r a l functional overview stm8l151xx, stm8l152xx 18/101 doc id 15962 rev 2 3.6 lcd (liquid crystal display) the liquid crystal display drives up to 4 common terminals and up to 28 segment terminals to drive up to 112 pixels. internal step-up converter to guarantee contrast control whatever v dd . static 1/2, 1/3, 1/4 duty supported. static 1/2, 1/3 bias supported. phase inversion to reduce power consumption and emi. up to 4 pixels which can programmed to blink. the lcd controller can operate in halt mode. note: unnecessary segments and common pins can be used as general i/o pins. 3.7 memories the stm8l15xxx devices have the following main features: up to 2 kbytes of ram the non-volatile memory is divided into three arrays: ? up to 32 kbytes of medium-density embedded flash program memory ? 1 kbyte of data eeprom ?option bytes. the eeprom embeds the error correction code (e cc) feature. it supp orts the read-while- write (rww): it is possible to execute the code from the program matrix while programming/erasing the data matrix. the option byte protects part of the flash program memory from write and readout piracy. 3.8 dma a 4-channel direct memory access controlle r (dma1) offers a memory-to-memory and peripherals-from/to-memory tr ansfer capability. the 4 chann els are shared between the following ips with dma capability: adc1, da c, i2c1, spi1, usart1, the 4 timers. 3.9 analog-to-digital converter 12-bit analog-to-digital converter (adc1) with 25 channels (including 1 fast channel), temperature sensor and internal reference voltage conversion time down to 1 s with f sysclk = 16 mhz programmable resolution programmable sampling time single and continuous mode of conversion scan capability: automatic conversion perfor med on a selected gr oup of anal og inputs analog watchdog triggered by timer note: adc1 can be served by dma1. stm8l151xx, stm8l152xx functional overview doc id 15962 rev 2 19/101 3.10 digital-to-analog converter (dac) 12-bit dac with output buffer synchronized update capability using tim4 dma capability external triggers for conversion input reference voltage v ref+ for better resolution note: dac can be served by dma1. 3.11 ultralow power comparators the stm8l15x embeds two comparators (comp1 and comp2) sharing the same current bias and voltage reference. the voltage reference can be internal or external (coming from an i/o). one comparator with fixed threshold (comp1). one comparator rail to rail with fast or slow mode (comp2). the threshold can be one of the following: ? dac output ? external i/o ? internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4) the two comparators can be used together to offer a window function. they can wake up from halt mode. 3.12 system configuration cont roller and routing interface the system configuration controller provides the capability to remap some alternate functions on different i/o ports. tim4 and adc1 dma channels can also be remapped. the highly flexible routing interface allows application software to control the routing of different i/os to the tim1 timer input captures. it also controls the routing of internal analog signals to adc1, comp1, comp2, dac and the internal reference voltage v refint . finally, it provides a set of registers for efficiently managing a set of dedicated i/os supporting up to 16 capacitive sensing ch annels using the proxsense tm technology. 3.13 timers stm8l15xxx devices contain one advanced control timer (tim1), two 16-bit general purpose timers (tim2 and tim3) and one 8-bit basic timer (tim4). all the timers can be served by dma1. ta bl e 3 compares the features of the advanced control, general-purpose and basic timers. functional overview stm8l151xx, stm8l152xx 20/101 doc id 15962 rev 2 3.13.1 tim1 - 16-bit ad vanced control timer this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-ti me control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and half-bridge driver. 16-bit up, down and up/down autoreload counter with 16-bit prescaler 3 independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output 1 additional capture/compare channel which is not connected to an external i/o synchronization module to control the timer with external signals break input to force timer outputs into a defined state 3 complementary outputs with adjustable dead time encoder mode interrupt capability on various events (cap ture, compare, overflow, break, trigger) 3.13.2 16-bit general purpose timers 16-bit autoreload (ar) up/down-counter 7-bit prescaler adjustable to fixed power of 2 ratios (1?128) 2 individually configurable capture/compare channels pwm mode interrupt capability on various events (cap ture, compare, overflow, break, trigger) synchronization with other timers or external signals (external clock, reset, trigger and enable) 3.13.3 8-bit basic timer the 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. it can be used for timebase generation with interrupt generation on timer overflow or for dac trigger generation. table 3. timer feature comparison timer counter resolution counter type prescaler factor dma1 request generation capture/compare channels complementary outputs tim1 16-bit up/down any integer from 1 to 65536 ye s 3 + 1 3 tim2 any power of 2 from 1 to 128 2 none tim3 tim4 8-bit up any power of 2 from 1 to 32768 0 stm8l151xx, stm8l152xx functional overview doc id 15962 rev 2 21/101 3.14 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. 3.14.1 window watchdog timer the window watchdog (wwdg) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.14.2 independent watchdog timer the independent watchdog peripheral (iwdg) can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the internal lsi rc clock source, and thus stays active even in case of a cpu clock failure. 3.15 beeper the beeper functi on outputs a signal on the beep pin for sound gener ation. the signal is in the range of 1, 2 or 4 khz. 3.16 communication interfaces 3.16.1 spi the serial peripheral interface (spi1) provides half/ full duplex synchronous serial communication with external devices. maximum speed: 8 mbit/s (f sysclk /2) both for master and slave full duplex synchronous transfers simplex synchronous transfers on 2 lines with a possible bidirectional data line master or slave operation - selectable by hardware or software hardware crc calculation slave/master selection input pin note: spi1 can be served by the dma1 controller. 3.16.2 i2c the i 2 c bus interface (i 2 c1) provides multi-master capab ility, and controls all i2c bus- specific sequencing, protocol, arbitration and timing. master, slave and multi-master capability standard mode up to 100 khz and fast speed modes up to 400 khz. 7-bit and 10-bit addressing modes. smbus 2.0 and pmbus support hardware crc calculation functional overview stm8l151xx, stm8l152xx 22/101 doc id 15962 rev 2 note: i 2 c1 can be served by the dma1 controller. 3.16.3 usart the usart interface (usart1) allows full duplex, asynchronous communications with external devices requiring an industry standard nrz asynchronous serial data format. it offers a very wide range of baud rates. 1 mbit/s full duplex sci spi1 emulation high precision baud rate generator smartcard emulation irda sir encoder decoder single wire half duplex mode note: usart1 can be served by the dma1 controller. 3.17 infrared (ir) interface the stm8l15x devices contain an infrared interface which can be used with an ir led for remote control functions. two timer output compare channels are used to generate the infrared remote control signals. 3.18 development support development tools development tools for the stm8 microcontrollers include: the stice emulation system offe ring tracing and code profiling the stvd high-level language debugger including c compiler, assembler and integrated development environment the stvp flash programming software the stm8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. single wire data interface (swim) and debug module the debug module with its single wire data interface (swim) permits non-intrusive real-time in-circuit debugging and fast memory programming. the single wire interface is used for direct access to the debugging module and memory programming. the interface can be activated in all device operation modes. the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, cpu operation can also be monitored in real- time by means of shadow registers. bootloader a bootloader is available to reprogram the flash memory using the usart1 interface. stm8l151xx, stm8l152xx pin description doc id 15962 rev 2 23/101 4 pin description figure 3. stm8l151gx 28-pin package pinout figure 4. stm8l151kx 32-pin package pinout (without lcd) 1. example given for the wfqfpn32 package. the pinout is the same for the lqfp32 package. figure 5. stm8l152kx 32-pin package pinout (with lcd) 1. example given for the wfqfpn32 package. the pinout is the same for the lqfp32 package. pd3 pb0 pb1 pb2 pd0 pd1 pd2 pa 5 v ss /v ssa /v ref- v dd /v dda /v ref+ nrst/pa1 pa 2 pa 4 pb6 pb5 pb4 pb3 pc0 pd4 pb7 pc4 pc3 pc2 pc1 pa 0 pc6 pc5 2 1 3 4 5 6 7 9 8 10 11 12 13 14 20 21 19 18 17 16 15 27 28 26 25 24 23 22 pa 3 1 2 3 4 5 6 7 8 9101112 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 pa5 v ss nrst/pa1 pa2 pa3 pa4 pa6 v dd pd3 pb0 pb1 pd0 pd1 pd2 pb3 pb2 pb5 pb4 pd4 pb7 pb6 pd7 pd6 pd5 pc0 pc3 pc2 pc1 pc4 pc5 pc6 pa0 1 2 3 4 5 6 7 8 9101112 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 pa5 v ss nrst/pa1 pa2 pa3 pa4 pa6 v dd pd3 pb0 pb1 vlcd pd1 pd2 pb3 pb2 pb5 pb4 pd4 pb7 pb6 pd7 pd6 pd5 pc0 pc3 pc2 pc1 pc4 pc5 pc6 pa0 pin description stm8l151xx, stm8l152xx 24/101 doc id 15962 rev 2 figure 6. stm8l151cx 48-pin pinout (without lcd) 1. reserved. must be tied to v dd . figure 7. stm8l152cx 48-pin pinout (with lcd) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 pa5 v ss /v ssa/ v ref- nrst/pa1 pa2 pa3 pa4 pa6 res. (1) pe0 pe1 pd1 pd2 pd3 pb0 pe3 pd0 pe5 pe4 pa7 v dd v dda v ref+ pe2 pb1 pb2 pc0 pc1 v ddio v ssio pc2 pc3 pc4 pc5 pc6 pc7 pe6 pe7 pb3 pb4 pb5 pb6 pb7 pf0 pd4 pd5 pd6 pd7 pa 0 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 pa5 v ss /v ssa/ v ref- nrst/pa1 pa2 pa3 pa4 pa6 vlcd pe0 pe1 pd1 pd2 pd3 pb0 pe3 pd0 pe5 pe4 pa7 v dd v dda v ref+ pe2 pb1 pb2 pc0 pc1 v ddio v ssio pc2 pc3 pc4 pc5 pc6 pc7 pe6 pe7 pb3 pb4 pb5 pb6 pb7 pf0 pd4 pd5 pd6 pd7 pa 0 stm8l151xx, stm8l152xx pin description doc id 15962 rev 2 25/101 legend / abbreviations for ta b l e 4 : type: i = input, o = output, s = power supply i/o level: ft = 5 v tolerant input level: cm = cmos output level: hs = high sink/source (20 ma) port and control configuration: input: float = floating, wpu = weak pull-up output: t= true open drain, od = open drain, pp = push-pull reset state is shown in bold . table 4. stm8l15x pin description pin number pin name type i/o level input output main function (after reset) default alternate function vfqfpn48 and lqfp48 wfqfpn32 wfqfpn28 floating wpu ext. interrupt high sink/source od pp 2 1 1 nrst/pa1 (1) i/o hs x x reset pa 1 322 pa2/osc_in/ [usart1_tx] (3) / [spi1_miso] (3) i/o x xxhsxx port a2 hse oscillator input / [usart1 transmit] / [spi1 master in- slave out] / 433 pa3/osc_out/ [usart1 _rx] (3) /[spi1_mosi] (3) i/o x xxhsxx port a3 hse oscillator output / [usart1 receive]/ [spi1 master out/slave in] / 5- - pa4/tim2_bkin/ lcd_com0 (2) /adc1_in2/ comp1_inp i/o x xxhsxx port a4 timer 2 - break input / lcd com 0 / adc1 input 2 / comparator 1 positive input -44 pa4/tim2_bkin/ [tim2_trig] (3) / lcd_com0 (2) / adc1_in2/comp1_inp i/o x xxhsxx port a4 timer 2 - break input / [timer 2 - trigger] / lcd_com 0 / adc1 input 2 / comparator 1 positive input 6- pa5/tim3_bkin/ lcd_com1 (2) /adc1_in1/ comp1_inp i/o x xxhsxx port a5 timer 3 - break input / lcd_com 1 / adc1 input 1/ comparator 1 positive input -55 pa5/tim3_bkin/ [tim3_trig] (3) / lcd_com1 (2) /adc1_in1/ comp1_inp i/o x xxhsxx port a5 timer 3 - break input / [timer 3 - trigger] / lcd_com 1 / adc1 input 1 / comparator 1 positive input 76 - pa 6 / [adc1_trig] (3) / lcd_com2 (2) /adc1_in0/ comp1_inp i/o x xxhsxx port a6 [adc1 - trigger] / lcd_com2 / adc1 input 0 / comparator 1 positive input pin description stm8l151xx, stm8l152xx 26/101 doc id 15962 rev 2 8 - - pa7/lcd_seg0 (2) i/o ft x xxhsxx port a7 lcd segment 0 24 13 12 pb0/tim2_ch1/ lcd_seg10 (2) / adc1_in18/comp1_inp i/o x xxhsxx port b0 timer 2 - channel 1 / lcd segment 10 / adc1_in18 / comparator 1 positive input 25 14 13 pb1/tim3_ch1/ lcd_seg11 (2) / adc1_in17/comp1_inp i/o x xxhsxx port b1 timer 3 - channel 1 / lcd segment 11 / adc1_in17 / comparator 1 positive input 26 15 14 pb2/ tim2_ch2/ lcd_seg12 (2) / adc1_in16/comp1_inp i/o x xxhsxx port b2 timer 2 - channel 2 / lcd segment 12 / adc1_in16/ comparator 1 positive input 27 - - pb3/tim2_trig/ lcd_seg13 (2) / adc1_in15/comp1_inp i/o x xxhsxx port b3 timer 2 - trigger / lcd segment 13 /adc1_in15 / comparator 1 positive input -16- pb3/ [tim2_trig] (3) / tim1_ch2n/lcd_seg13 (2) /adc1_in15/ comp1_inp i/o x xxhsxx port b3 [timer 2 - trigger] / timer 1 inverted channel 2 / lcd segment 13 / adc1_in15 / comparator 1 positive input --15 pb3/ [tim2_trig] (3) / tim1_ch1n/ lcd_seg13 (2) / adc1_in15/rtc_alarm /comp1_inp i/o x xxhsxx port b3 [timer 2 - trigger] / timer 1 inverted channel 1/ lcd segment 13 / adc1_in15 / rtc alarm/ comparator 1 positive input 28 - - pb4/ [spi1_nss] (3) / lcd_seg14 (2) / adc1_in14/comp1_inp i/o x xxhsxx port b4 [spi1 master/slave select] / lcd segment 14 / adc1_in14 / comparator 1 positive input -1716 pb4/ [spi1_nss] (3) / lcd_seg14 (2) / adc1_in14/ comp1_inp/dac_out i/o x xxhsxx port b4 [spi1 master/slave select] / lcd segment 14 / adc1_in14 / dac output / comparator 1 positive input 29 - - pb5/ [spi1_sck] (3) / lcd_seg15 (2) / adc1_in13/comp1_inp i/o x xxhsxx port b5 [spi1 clock] / lcd segment 15 / adc1_in13 / comparator 1 positive input -1817 pb5/ [spi1_sck] (3) / lcd_seg15 (2) / adc1_in13/dac_out/ comp1_inp i/o x xxhsxx port b5 [spi1 clock] / lcd segment 15 / adc1_in13 / dac output/ comparator 1 positive input table 4. stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function vfqfpn48 and lqfp48 wfqfpn32 wfqfpn28 floating wpu ext. interrupt high sink/source od pp stm8l151xx, stm8l152xx pin description doc id 15962 rev 2 27/101 30 - - pb6/[ spi1_mosi] (3) / lcd_seg16 (2) / adc1_in12/comp1_inp i/o x xxhsxx port b6 [spi1 master out/slave in] / lcd segment 16 / adc1_in12 / comparator 1 positive input -1918 pb6/ [spi1_mosi] (3) / lcd_seg16 (2) / adc1_in12/comp1_inp/ dac_out i/o x xxhsxx port b6 [spi1 master out] / slave in / lcd segment 16 / adc1_in12 / dac output / comparator 1 positive input 31 20 19 pb7/ [spi1_miso] (3) / lcd_seg17 (2) / adc1_in11/comp1_inp i/o x xxhsxx port b7 [spi1 master in- slave out] / lcd segment 17 / adc1_in11 / comparator 1 positive input 37 25 21 pc0/i2c1_sda i/o ft x xt (4) port c0 i2c1 data 38 26 22 pc1/i2c1_scl i/o ft x xt (4) port c1 i2c1 clock 41 27 23 pc2/ [usart1_rx] (3) / lcd_seg22/adc1_in6/ comp1_inp/vref_out i/o x xxhsxx port c2 [usart1 receive] / lcd segment 22 / adc1_in6 / comparator 1 positive input / voltage reference output 42 28 24 pc3/ [usart1_tx] (3) / lcd_seg23 (2) / adc1_in5/comp1_inp/ comp2_inm i/o x xxhsxx port c3 [usart1 transmit] / lcd segment 23 / adc1_in5 / comparator 1 positive input / comparator 2 negative input 43 29 25 pc4/ [usart1_ck] (3) / i2c1_smb/cco/ lcd_seg24 (2) / adc1_in4/comp2_inm/ comp1_inp i/o x xxhsxx port c4 [usart1 synchronous clock] / i2c1_smb / configurable clock output / lcd segment 24 / adc1_in4 / comparator 2 negative input / comparator 1 positive input 44 30 26 pc5/osc32_in / [spi1_nss] (3) / [usart1_tx] (3) i/o x x x hs x x port c5 lse oscillator input / [spi1 master/slave select] / [usart1 transmit] 45 31 27 pc6/osc32_out/ [spi1_sck] (3) / [usart1_rx] (3) i/o x x x hs x x port c6 lse oscillator output / [spi1 clock] / [usart1 receive] 46 - - pc7/lcd_seg25 (2) / adc1_in3/comp2_inm/ comp1_inp i/o x x x hs x x port c7 lcd segment 25 /adc1_in3/ comparator negative input / comparator 1 positive input table 4. stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function vfqfpn48 and lqfp48 wfqfpn32 wfqfpn28 floating wpu ext. interrupt high sink/source od pp pin description stm8l151xx, stm8l152xx 28/101 doc id 15962 rev 2 20 - 8 pd0/tim3_ch2/ [adc1_trig] (3) / lcd_seg7 (2) /adc1_in2 2/comp2_inp/ comp1_inp i/o x x x hs x x port d0 timer 3 - channel 2 / [adc1_trigger] / lcd segment 7 / adc1_in22 / comparator 2 positive input / comparator 1 positive input -9- pd0/tim3_ch2/ [adc1_trig] (3) / adc1_in22/comp2_inp/ comp1_inp i/o x x x hs x x port d0 (5) timer 3 - channel 2 / [adc1_trigger] / adc1_in22 / comparator 2 positive input / comparator 1 positive input 21 - - pd1/tim3_trig/ lcd_com3 (2) / adc1_in21/comp2_inp/ comp1_inp i/o x x x hs x x port d1 timer 3 - trigge r / lcd_com3 / adc1_in21 / comparator 2 positive input / comparator 1 positive input -10- pd1/tim1_ch3n/[ tim3_t rig ] (3) / lcd_com3 (2) / adc1_in21/comp2_inp/ comp1_inp i/o x x x hs x x port d1 [timer 3 - trigger]/ tim1 inverted channel 3 / lcd_com3/ adc1_in21 / comparator 2 positive input / comparator 1 positive input --9 pd1/tim1_ch3/[ tim3_tr ig ] (3) /lcd_com3 (2) / adc1_in21/comp2_inp/ comp1_inp i/o x x x hs x x port d1 timer 1 channel 3 / [timer 3 - trigger] / lcd_com3/ adc1_in21 / comparator 2 positive input / comparator 1 positive input 22 11 10 pd2/tim1_ch1 /lcd_seg8 (2) / adc1_in20/comp1_inp i/o x x x hs x x port d2 timer 1 - channel 1 / lcd segment 8 / adc1_in20 / comparator 1 positive input 23 12 - pd3/ tim1_trig/ lcd_seg9 (2) /adc1_in1 9/comp1_inp i/o x x x hs x x port d3 timer 1 - trigger / lcd segment 9 / adc1_in19 / comparator 1 positive input --11 pd3/ tim1_trig/ lcd_seg9 (2) / adc1_in19/tim1_bkin/ comp1_inp/ rtc_calib i/o x x x hs x x port d3 timer 1 - trigger / lcd segment 9 / adc1_in19 / timer 1 break input / rtc calibration / comparator 1 positive input 33 21 20 pd4/tim1_ch2 /lcd_seg18 (2) / adc1_in10/comp1_inp i/o x x x hs x x port d4 timer 1 - channel 2 / lcd segment 18 / adc1_in10/ comparator 1 positive input table 4. stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function vfqfpn48 and lqfp48 wfqfpn32 wfqfpn28 floating wpu ext. interrupt high sink/source od pp stm8l151xx, stm8l152xx pin description doc id 15962 rev 2 29/101 34 22 - pd5/tim1_ch3 /lcd_seg19 (2) / adc1_in9/comp1_inp i/o x x x hs x x port d5 timer 1 - channel 3 / lcd segment 19 / adc1_in9/ comparator 1 positive input 35 23 - pd6/tim1_bkin /lcd_seg20 (2) / adc1_in8/rtc_calib/ vref_out/ comp1_inp i/o x x x hs x x port d6 timer 1 - break input / lcd segment 20 / adc1_in8 / rtc calibration / voltage reference output / comparator 1 positive input 36 24 - pd7/tim1_ch1n /lcd_seg21 (2) / adc1_in7/rtc_alarm/ vref_out/ comp1_inp i/o x x x hs x x port d7 timer 1 - inverted channel 1/ lcd segment 21 / adc1_in7 / rtc alarm / voltage reference output /comparator 1 positive input 14 - - pe0/lcd_seg1 (2) i/o ft x x x hs x x port e0 lcd segment 1 15 - - pe1/tim1_ch2n /lcd_seg2 (2) i/o x x x hs x x port e1 timer 1 - inverted channel 2 / lcd segment 2 16 - - pe2/tim1_ch3n /lcd_seg3 (2) i/o x xxhsxx port e2 timer 1 - inverted channel 3 / lcd segment 3 17 - - pe3/lcd_seg4 (2) i/o x xxhsxx port e3 lcd segment 4 18 - - pe4/lcd_seg5 (2) i/o x xxhsxx port e4 lcd segment 5 19 - - pe5/lcd_seg6 (2) / adc1_in23/comp2_inp/ comp1_inp i/o x xxhsxx port e5 lcd segment 6 / adc1_in23 / comparator 2 positive input / comparator 1 positive input 47 - - pe6/lcd_seg26 (2) / pvd_in i/o x xxhsxx port e6 lcd segment 26/pvd_in 48 - - pe7/lcd_seg27 (2) i/o x xxhsxx port e7 lcd segment 27 32 - - pf0/adc1_in24/ dac_out i/o x xxhsxx port f0 adc1_in24 / dac_out 13 9 - vlcd (2) s lcd booster external capacitor 13 - - reserved (5) reserved. must be tied to v dd 10 - - v dd s digital power supply 11 - - v dda s analog supply voltage 12 - - v ref+ s adc1 and dac positive voltage reference table 4. stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function vfqfpn48 and lqfp48 wfqfpn32 wfqfpn28 floating wpu ext. interrupt high sink/source od pp pin description stm8l151xx, stm8l152xx 30/101 doc id 15962 rev 2 4.1 system configuration options as shown in table 4: stm8l15x pin description , some alternate functions can be remapped on different i/o ports by programming one of the two remapping registers described in the ? routing interface (ri) and system configuration controller? section in the stm8l15xxx reference manual (rm0031). -87v dd/ v dda/ v ref+ s digital power supply / analog supply voltage / adc1 positive voltage reference 976v ss /v ssa/ v ref- s i/o ground / analog ground voltage / adc1 negative voltage reference 39 - - v ddio s ios supply voltage 40 - - v ssio s ios ground voltage 13228 pa 0 / [usart1_ck] (3) / swim/beep/ir_tim (6) i/o x xx hs (6) xx port a0 [usart1 synchronous clock] (3) / swim input and output / beep output / infrared timer out- put 1. when the pa1/nrst pin is used as general purpose (pa1), it can be configured onl y as output push-pull, not as a general purpose input. refer to section configuring nrst/pa1 pi n as general purpose output in the stm8l15x reference manual (rm0031). 2. available on stm8l152xx devices only. 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it i ndicates an exclusive choice not a duplication of the function). 4. in the open-drain output column, ?t? defines a true open-drain i/o (p-buffer and protection diode to v dd are not implemented). 5. available on stm8l151xx devices only. 6. high sink led driver capability available on pa0. table 4. stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function vfqfpn48 and lqfp48 wfqfpn32 wfqfpn28 floating wpu ext. interrupt high sink/source od pp stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 31/101 5 memory and register map 5.1 memory mapping the memory map is shown in figure 8 . figure 8. memory map 1. table 5 lists the boundary addresses for each memory si ze. the top of the stack is at the ram end address. 2. refer to table 7 for an overview of hardware register mapping, to table 6 for details on i/o port hardware registers, and to table 8 for information on cpu/swim/debug module controller registers. gpio and peripheral registers 0x00 0000 reserved medium-density (up to 32 kbytes) reset and interrupt vectors 0x00 1000 0x00 13ff ram 0x00 07ff (2 kbytes) (1) (513 bytes) (1) 0x00 1400 data eeprom 0x00 4800 0x00 48ff 0x00 4900 0x00 7fff 0x00 8000 0x00 ffff 0x00 0800 0x00 0fff 0x00 47ff 0x00 7eff 0x00 8080 0x00 807f 0x00 7f00 reserved reserved including stack (1 kbyte) option bytes 0x00 49ff 0x00 5000 0x00 57ff 0x00 5800 reserved 0x00 59ff boot rom 0x00 6000 0x00 67ff (2 kbytes) 0x00 7000 reserved cpu/swim/debug/itc registers 0x00 5000 gpio ports 0x00 5050 flash 0x00 50c0 itc-exti 0x00 50d3 rst 0x00 50e0 clk 0x00 50f3 wwdg 0x00 5210 iwdg 0x00 5230 beep 0x00 5250 rtc 0x00 5280 spi1 0x00 52b0 i2c1 0x00 52e0 usart1 tim2 tim3 tim1 tim4 irtim adc1 0x00 5070 dma1 syscfg dac lcd ri 0x00 509e 0x00 50a0 0x00 50b0 0x00 5140 0x00 5200 0x00 52ff 0x00 5340 0x00 5380 0x00 5400 0x00 5430 0x00 5440 comp flash program memory memory and register map stm8l151xx, stm8l152xx 32/101 doc id 15962 rev 2 5.2 register map table 5. flash and ram boundary addresses memory area size start address end address ram 2 kbytes 0x00 0000 0x00 07ff flash program memory 16 kbytes 0x00 8000 0x00 bfff 32 kbytes 0x00 8000 0x00 ffff table 6. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0x00 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0x00 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0x00 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0x00 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x00 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0x00 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 33/101 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0x00 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 table 6. i/o port hardware register map (continued) address block register label register name reset status table 7. general hardware register map address block register label register name reset status 0x00 501e to 0x00 5049 reserved area (44 bytes) 0x00 5050 flash flash_cr1 flash control register 1 0x00 0x00 5051 flash_cr2 flash control register 2 0x00 0x00 5052 flash _pukr flash program memory unprotection key register 0x00 0x00 5053 flash _dukr data eeprom unprotection ke y register 0x00 0x00 5054 flash _iapsr flash in-application programming status register 0x00 0x00 5065 to 0x00 506f reserved area (11 bytes) memory and register map stm8l151xx, stm8l152xx 34/101 doc id 15962 rev 2 0x00 5070 dma1 dma1_gcsr dma1 global configuration & status register 0xfc 0x00 5071 dma1_gir1 dma1 global interrupt register 1 0x00 0x00 5072 to 0x00 5074 reserved area (3 bytes) 0x00 5075 dma1_c0cr dma1 channel 0 configuration register 0x00 0x00 5076 dma1_c0spr dma1 channel 0 status & priority register 0x00 0x00 5077 dma1_c0ndtr dma1 number of data to transfer register (channel 0) 0x00 0x00 5078 dma1_c0parh dma1 peripheral address high register (channel 0) 0x52 0x00 5079 dma1_c0parl dma1 peripheral address low register (channel 0) 0x00 0x00 507a reserved area (1 byte) 0x00 507b dma1_c0m0arh dma1 memory 0 address high register (channel 0) 0x00 0x00 507c dma1_c0m0arl dma1 memory 0 address low register (channel 0) 0x00 0x00 507d to 0x00 507e reserved area (2 bytes) 0x00 507f dma1_c1cr dma1 channel 1 configuration register 0x00 0x00 5080 dma1_c1spr dma1 channel 1 status & priority register 0x00 0x00 5081 dma1_c1ndtr dma1 number of data to transfer register (channel 1) 0x00 0x00 5082 dma1_c1parh dma1 peripheral address high register (channel 1) 0x52 0x00 5083 dma1_c1parl dma1 peripheral address low register (channel 1) 0x00 table 7. general hardware register map (continued) address block register label register name reset status stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 35/101 0x00 5084 dma1 reserved area (1 byte) 0x00 5085 dma1_c1m0arh dma1 memory 0 address high register (channel 1) 0x00 0x00 5086 dma1_c1m0arl dma1 memory 0 address low register (channel 1) 0x00 0x00 5087 0x00 5088 reserved area (2 bytes) 0x00 5089 dma1_c2cr dma1 channel 2 configuration register 0x00 0x00 508a dma1_c2spr dma1 channel 2 status & priority register 0x00 0x00 508b dma1_c2ndtr dma1 number of data to transfer register (channel 2) 0x00 0x00 508c dma1_c2parh dma1 peripheral address high register (channel 2) 0x52 0x00 508d dma1_c2parl dma1 peripheral address low register (channel 2) 0x00 0x00 508e reserved area (1 byte) 0x00 508f dma1_c2m0arh dma1 memory 0 address high register (channel 2) 0x00 0x00 5090 dma1_c2m0arl dma1 memory 0 address low register (channel 2) 0x00 0x00 5091 0x00 5092 reserved area (2 bytes) 0x00 5093 dma1_c3cr dma1 channel 3 configuration register 0x00 0x00 5094 dma1_c3spr dma1 channel 3 status & priority register 0x00 0x00 5095 dma1_c3ndtr dma1 number of data to transfer register (channel 3) 0x00 0x00 5096 dma1_c3parh_ c3m1arh dma1 peripheral address high register (channel 3) 0x40 0x00 5097 dma1_c3parl_ c3m1arl dma1 peripheral address low register (channel 3) 0x00 0x00 5098 reserved area (1 byte) 0x00 5099 dma1_c3m0arh dma1 memory 0 address high register (channel 3) 0x00 0x00 509a dma1_c3m0arl dma1 memory 0 address low register (channel 3) 0x00 0x00 509b to 0x00 509d reserved area (3 bytes) 0x00 509e syscfg syscfg_rmpcr1 remapping register 1 0x00 0x00 509f syscfg_rmpcr2 remapping register 2 0x00 table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151xx, stm8l152xx 36/101 doc id 15962 rev 2 0x00 50a0 itc - exti exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external inte rrupt control register 2 0x00 0x00 50a2 exti_cr3 external inte rrupt control register 3 0x00 0x00 50a3 exti_sr1 external interrupt status register 1 0x00 0x00 50a4 exti_sr2 external interrupt status register 2 0x00 0x00 50a5 exti_conf external interrupt port select register 0x00 0x00 50a6 wfe wfe_cr1 wfe control register 1 0x00 0x00 50a7 wfe_cr2 wfe control register 2 0x00 0x00 50a8 wfe_cr3 wfe control register 3 0x00 0x00 50a9 to 0x00 50af reserved area (7 bytes) 0x00 50b0 rst rst_cr reset control register 0x00 0x00 50b1 rst_sr reset status register 0x01 0x00 50b2 pwr pwr_csr1 power control and status register 1 0x00 0x00 50b3 pwr_csr2 power control and status register 2 0x00 0x00 50b4 to 0x00 50bf reserved area (12 bytes) 0x00 50c0 clk clk_divr clock master divider register 0x03 0x00 50c1 clk_crtcr clock rtc register 0x00 0x00 50c2 clk_ickr internal clock control register 0x11 0x00 50c3 clk_pckenr1 peripheral clock gating register 1 0x00 0x00 50c4 clk_pckenr2 peripheral clock gating register 2 0x00 0x00 50c5 clk_ccor configurable clock control register 0x00 0x00 50c6 clk_eckr external clock control register 0x00 0x00 50c7 clk_scsr system clock status register 0x01 0x00 50c8 clk_swr system clock switch register 0x01 0x00 50c9 clk_swcr clock switch control register 0bxxxx0000 0x00 50ca clk_cssr clock security system register 0x00 0x00 50cb clk_cbeepr clock beep register 0x00 0x00 50cc clk_hsicalr hsi calibration register 0x00 0x00 50cd clk_hsitrimr hsi clock calibration trimming register 0x00 0x00 50ce clk_hsiunlckr hsi unlock register 0x00 0x00 50cf clk_regcsr main regulator control status register 0bxx11100x table 7. general hardware register map (continued) address block register label register name reset status stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 37/101 0x00 50d0 to 0x00 50d2 reserved area (3 bytes) 0x00 50d3 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d4 wwdg_wr wwdr window register 0x7f 0x00 50d5 to 00 50df reserved area (11 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0x 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 beep beep_csr1 beep control/stat us register 1 0x00 0x00 50f1 0x00 50f2 reserved area (2 bytes) 0x00 50f3 beep_csr2 beep control/ status regi ster 2 0x1f 0x00 50f4 to 0x00 513f reserved area (76 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151xx, stm8l152xx 38/101 doc id 15962 rev 2 0x00 5140 rtc rtc_tr1 time register 1 0x00 0x00 5141 rtc_tr2 time register 2 0x00 0x00 5142 rtc_tr3 time register 3 0x00 0x00 5143 reserved area (1 byte) 0x00 5144 rtc_dr1 date register 1 0x00 0x00 5145 rtc_dr2 date register 2 0x00 0x00 5146 rtc_dr3 date register 3 0x00 0x00 5147 reserved area (1 byte) 0x00 5148 rtc_cr1 control register 1 0x00 0x00 5149 rtc_cr2 control register 2 0x00 0x00 514a rtc_cr3 control register 3 0x00 0x00 514b reserved area (1 byte) 0x00 514c rtc_isr1 initialization and status register 1 0x00 0x00 514d rtc_isr2 initialization and status register 2 0x00 0x00 514e 0x00 514f reserved area (2 bytes) 0x00 5150 rtc_sprerh synchronous prescaler register high - 0x00 5151 rtc_sprerl synchronous prescaler register low - 0x00 5152 rtc_aprer asynchronous prescaler register - 0x00 5153 reserved area (1 byte) 0x00 5154 rtc_wutrh wakeup timer register high - 0x00 5155 rtc_wutrl wakeup timer register low - 0x00 5156 to 0x00 5158 reserved area (3 bytes) 0x00 5159 rtc_wpr write protection register 0x00 0x00 515a 0x00 515b reserved area (2 bytes) 0x00 515c rtc_alrmar1 alarm a register 1 0x00 0x00 515d rtc_alrmar2 alarm a register 2 0x00 0x00 515e rtc_alrmar3 alarm a register 3 0x00 0x00 515f rtc_alrmar4 alarm a register 4 0x00 0x00 5160 to 0x00 51ff reserved area (160 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 39/101 0x00 5200 spi1 spi1_cr1 spi1 control register 1 0x00 0x00 5201 spi1_cr2 spi1 control register 2 0x00 0x00 5202 spi1_icr spi1 interrupt control register 0x00 0x00 5203 spi1_sr spi1 status register 0x02 0x00 5204 spi1_dr spi1 data register 0x00 0x00 5205 spi1_crcpr spi1 crc polynomial register 0x07 0x00 5206 spi1_rxcrcr spi1 rx crc register 0x00 0x00 5207 spi1_txcrcr spi1 tx crc register 0x00 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i2c1 i2c1_cr1 i2c1 control register 1 0x00 0x00 5211 i2c1_cr2 i2c1 control register 2 0x00 0x00 5212 i2c1_freqr i2c1 frequency register 0x00 0x00 5213 i2c1_oarl i2c1 own address register low 0x00 0x00 5214 i2c1_oarh i2c1 own address register high 0x00 0x00 5215 reserved (1 byte) 0x00 5216 i2c1_dr i2c1 data register 0x00 0x00 5217 i2c1_sr1 i2c1 status register 1 0x00 0x00 5218 i2c1_sr2 i2c1 status register 2 0x00 0x00 5219 i2c1_sr3 i2c1 status register 3 0x0x 0x00 521a i2c1_itr i2c1 interrupt control register 0x00 0x00 521b i2c1_ccrl i2c1 clock control register low 0x00 0x00 521c i2c1_ccrh i2c1 clock control register high 0x00 0x00 521d i2c1_triser i2c1 trise register 0x02 0x00 521e i2c1_pecr i2c1 packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151xx, stm8l152xx 40/101 doc id 15962 rev 2 0x00 5230 usart1 usart1_sr usart1 status register 0xc0 0x00 5231 usart1_dr usart1 data register undefined 0x00 5232 usart1_brr1 usart1 baud rate register 1 0x00 0x00 5233 usart1_brr2 usart1 baud rate register 2 0x00 0x00 5234 usart1_cr1 usart1 control register 1 0x00 0x00 5235 usart1_cr2 usart1 control register 2 0x00 0x00 5236 usart1_cr3 usart1 control register 3 0x00 0x00 5237 usart1_cr4 usart1 control register 4 0x00 0x00 5238 usart1_cr5 usart1 control register 5 0x00 0x00 5239 usart1_gtr usart1 guard time register 0x00 0x00 523a usart1_pscr usart1 prescaler register 0x00 0x00 523b to 0x00 524f reserved area (21 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 41/101 0x00 5250 tim2 tim2_cr1 tim2 contro l register 1 0x00 0x00 5251 tim2_cr2 tim2 control register 2 0x00 0x00 5252 tim2_smcr tim2 slave mode control register 0x00 0x00 5253 tim2_etr tim2 external trigger register 0x00 0x00 5254 tim2_der tim2 dma1 request enable register 0x00 0x00 5255 tim2_ier tim2 inte rrupt enable register 0x00 0x00 5256 tim2_sr1 tim2 status register 1 0x00 0x00 5257 tim2_sr2 tim2 status register 2 0x00 0x00 5258 tim2_egr tim2 even t generation register 0x00 0x00 5259 tim2_ccmr1 tim2 captur e/compare mode register 1 0x00 0x00 525a tim2_ccmr2 tim2 capture/ compare mode register 2 0x00 0x00 525b tim2_ccer1 tim2 capture/ compare enable register 1 0x00 0x00 525c tim2_cntrh tim2 counter high 0x00 0x00 525d tim2_cntrl tim2 counter low 0x00 0x00 525e tim2_pscr tim2 prescaler register 0x00 0x00 525f tim2_arrh tim2 auto-reload register high 0xff 0x00 5260 tim2_arrl tim2 auto-reload register low 0xff 0x00 5261 tim2_ccr1h tim2 capture/compare register 1 high 0x00 0x00 5262 tim2_ccr1l tim2 captur e/compare register 1 low 0x00 0x00 5263 tim2_ccr2h tim2 capture/compare register 2 high 0x00 0x00 5264 tim2_ccr2l tim2 captur e/compare register 2 low 0x00 0x00 5265 tim2_bkr tim2 break register 0x00 0x00 5266 tim2_oisr tim2 output idle state register 0x00 0x00 5267 to 0x00 527f reserved area (25 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151xx, stm8l152xx 42/101 doc id 15962 rev 2 0x00 5280 tim3 tim3_cr1 tim3 contro l register 1 0x00 0x00 5281 tim3_cr2 tim3 control register 2 0x00 0x00 5282 tim3_smcr tim3 slave mode control register 0x00 0x00 5283 tim3_etr tim3 external trigger register 0x00 0x00 5284 tim3_der tim3 dma1 request enable register 0x00 0x00 5285 tim3_ier tim3 inte rrupt enable register 0x00 0x00 5286 tim3_sr1 tim3 status register 1 0x00 0x00 5287 tim3_sr2 tim3 status register 2 0x00 0x00 5288 tim3_egr tim3 even t generation register 0x00 0x00 5289 tim3_ccmr1 tim3 captur e/compare mode register 1 0x00 0x00 528a tim3_ccmr2 tim3 captur e/compare mode register 2 0x00 0x00 528b tim3_ccer1 tim3 capture/ compare enable register 1 0x00 0x00 528c tim3_cntrh tim3 counter high 0x00 0x00 528d tim3_cntrl tim3 counter low 0x00 0x00 528e tim3_pscr tim3 prescaler register 0x00 0x00 528f tim3_arrh tim3 auto-reload register high 0xff 0x00 5290 tim3_arrl tim3 auto-reload register low 0xff 0x00 5291 tim3_ccr1h tim3 captur e/compare register 1 high 0x00 0x00 5292 tim3_ccr1l tim3 captur e/compare register 1 low 0x00 0x00 5293 tim3_ccr2h tim3 captur e/compare register 2 high 0x00 0x00 5294 tim3_ccr2l tim3 captur e/compare register 2 low 0x00 0x00 5295 tim3_bkr tim3 break register 0x00 0x00 5296 tim3_oisr tim3 output idle state register 0x00 0x00 5297 to 0x00 52af reserved area (25 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 43/101 0x00 52b0 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 52b1 tim1_cr2 tim1 control register 2 0x00 0x00 52b2 tim1_smcr tim1 slave mode control register 0x00 0x00 52b3 tim1_etr tim1 external trigger register 0x00 0x00 52b4 tim1_der tim1 dma1 request enable register 0x00 0x00 52b5 tim1_ier tim1 interrupt enable register 0x00 0x00 52b6 tim1_sr1 tim1 status register 1 0x00 0x00 52b7 tim1_sr2 tim1 status register 2 0x00 0x00 52b8 tim1_egr tim1 event generation register 0x00 0x00 52b9 tim1_ccmr1 tim1 captur e/compare mode register 1 0x00 0x00 52ba tim1_ccmr2 tim1 capture/ compare mode register 2 0x00 0x00 52bb tim1_ccmr3 tim1 capture/ compare mode register 3 0x00 0x00 52bc tim1_ccmr4 tim1 captur e/compare mode register 4 0x00 0x00 52bd tim1_ccer1 tim1 capture/ compare enable register 1 0x00 0x00 52be tim1_ccer2 tim1 capture/ compare enable register 2 0x00 0x00 52bf tim1_cntrh tim1 counter high 0x00 0x00 52c0 tim1_cntrl tim1 counter low 0x00 0x00 52c1 tim1_pscrh tim1 prescaler register high 0x00 0x00 52c2 tim1_pscrl tim1 prescaler register low 0x00 0x00 52c3 tim1_arrh tim1 auto-reload register high 0xff 0x00 52c4 tim1_arrl tim1 auto-reload register low 0xff 0x00 52c5 tim1_rcr tim1 repet ition counter register 0x00 0x00 52c6 tim1_ccr1h tim1 capture/ compare register 1 high 0x00 0x00 52c7 tim1_ccr1l tim1 captur e/compare register 1 low 0x00 0x00 52c8 tim1_ccr2h tim1 capture/ compare register 2 high 0x00 0x00 52c9 tim1_ccr2l tim1 captur e/compare register 2 low 0x00 0x00 52ca tim1_ccr3h tim1 capture/ compare register 3 high 0x00 0x00 52cb tim1_ccr3l tim1 captur e/compare register 3 low 0x00 0x00 52cc tim1_ccr4h tim1 capture/ compare register 4 high 0x00 0x00 52cd tim1_ccr4l tim1 captur e/compare register 4 low 0x00 0x00 52ce tim1_bkr tim1 break register 0x00 0x00 52cf tim1_dtr tim1 dead-time register 0x00 0x00 52d0 tim1_oisr tim1 output idle state register 0x00 0x00 52d1 tim1_dcr1 dma1 control register 1 table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151xx, stm8l152xx 44/101 doc id 15962 rev 2 0x00 52d2 tim1_dcr2 tim1 dma1 control register 2 0x00 0x00 52d3 tim1_dma1r tim1 dma1 address for burst mode 0x00 0x00 52d4 to 0x00 52df reserved area (12 bytes) 0x00 52e0 tim4 tim4_cr1 tim4 contro l register 1 0x00 0x00 52e1 tim4_cr2 tim4 control register 2 0x00 0x00 52e2 tim4_smcr tim4 slave mode control register 0x00 0x00 52e3 tim4_der tim4 dma1 request enable register 0x00 0x00 52e4 tim4_ier tim4 interrupt enable register 0x00 0x00 52e5 tim4_sr1 tim4 status register 1 0x00 0x00 52e6 tim4_egr tim4 event generation register 0x00 0x00 52e7 tim4_cntr tim4 counter 0x00 0x00 52e8 tim4_pscr tim4 prescaler register 0x00 0x00 52e9 tim4_arr tim4 auto-reload register 0x00 0x00 52ea to 0x00 52fe reserved area (21 bytes) 0x00 52ff irtim ir_cr infrared control register 0x00 0x00 5300 to 0x00 533f reserved area (64 bytes) 0x00 5340 adc1 adc1_cr1 adc1 configuration register 1 0x00 0x00 5341 adc1_cr2 adc1 configuration register 2 0x00 0x00 5342 adc1_cr3 adc1 configuration register 3 0x1f 0x00 5343 adc1_sr adc1 status register 0x00 0x00 5344 adc1_drh adc1 data register high 0x00 0x00 5345 adc1_drl adc1 data register low 0x00 0x00 5346 adc1_htrh adc1 high threshold register high 0x0f 0x00 5347 adc1_htrl adc1 high threshold register low 0xff 0x00 5348 adc1_ltrh adc1 low threshold register high 0x00 0x00 5349 adc1_ltrl adc1 low threshold register low 0x00 0x00 534a adc1_sqr1 adc1 channel sequence 1 register 0x00 0x00 534b adc1_sqr2 adc1 channel sequence 2 register 0x00 0x00 534c adc1_sqr3 adc1 channel sequence 3 register 0x00 0x00 534d adc1_sqr4 adc1 channel sequence 4 register 0x00 table 7. general hardware register map (continued) address block register label register name reset status stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 45/101 0x00 534e adc1 adc1_trigr1 adc1 trigger disable 1 0x00 0x00 534f adc1_trigr2 adc1 trigger disable 2 0x00 0x00 5350 adc1_trigr3 adc1 trigger disable 3 0x00 0x00 5351 adc1_trigr4 adc1 trigger disable 4 0x00 0x00 5352 to 0x00 537f reserved area (46 bytes) 0x00 5380 dac dac_cr1 dac control register 1 0x00 0x00 5381 dac_cr2 dac control register 2 0x00 0x00 5382 to 0x00 5383 reserved area (2 bytes) 0x00 5384 dac_swtrigr dac software trigger register 0x00 0x00 5385 dac_sr dac status register 0x00 0x00 5386 to 0x00 5387 reserved area (2 bytes) 0x00 5388 dac_rdhrh dac right aligned data holding register high 0x00 0x00 5389 dac_rdhrl dac right aligned data holding register low 0x00 0x00 538a to 0x00 538b reserved area (2 bytes) 0x00 538c dac_ldhrh dac left aligned data holding register high 0x00 0x00 538d dac_ldhrl dac left aligned data holding register low 0x00 0x00 538e to 0x00 538f reserved area (2 bytes) 0x00 5390 dac_dhr8 dac 8-bit data holding register 0x00 0x00 5391 to 0x00 53ab reserved area (27 bytes) 0x00 53ac dac_dorh dac data output register high 0x00 0x00 53ad dac_dorl dac data output register low 0x00 0x00 53ae to 0x00 53ff reserved area (82 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151xx, stm8l152xx 46/101 doc id 15962 rev 2 0x00 5400 lcd lcd_cr1 lcd control register 1 0x00 0x00 5401 lcd_cr2 lcd control register 2 0x00 0x00 5402 lcd_cr3 lcd control register 3 0x00 0x00 5403 lcd_frq lcd frequency selection register 0x00 0x00 5404 lcd_pm0 lcd port mask register 0 0x00 0x00 5405 lcd_pm1 lcd port mask register 1 0x00 0x00 5406 lcd_pm2 lcd port mask register 2 0x00 0x00 5407 lcd_pm3 lcd port mask register 3 0x00 0x00 5408 to 0x00 540b lcd reserved area (4 bytes) 0x00 540c lcd_ram0 lcd display memory 0 0x00 0x00 540d lcd_ram1 lcd display memory 1 0x00 0x00 540e lcd_ram2 lcd display memory 2 0x00 0x00 540f lcd_ram3 lcd display memory 3 0x00 0x00 5410 lcd_ram4 lcd display memory 4 0x00 0x00 5411 lcd_ram5 lcd display memory 5 0x00 0x00 5412 lcd_ram6 lcd display memory 6 0x00 0x00 5413 lcd_ram7 lcd display memory 7 0x00 0x00 5414 lcd_ram8 lcd display memory 8 0x00 0x00 5415 lcd_ram9 lcd display memory 9 0x00 0x00 5416 lcd_ram10 lcd display memory 10 0x00 0x00 5417 lcd_ram11 lcd display memory 11 0x00 0x00 5418 lcd_ram12 lcd display memory 12 0x00 0x00 5419 lcd_ram13 lcd display memory 13 0x00 0x00 541a to 0x00 542f reserved area (22 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 47/101 0x00 5430 ri reserved area (1 byte) 0x00 0x00 5431 ri_icr1 timer input capture routing register 1 0x00 0x00 5432 ri_icr2 timer input capture routing register 2 0x00 0x00 5433 ri_ioir1 i/o input register 1 undefined 0x00 5434 ri_ioir2 i/o input register 2 undefined 0x00 5435 ri_ioir3 i/o input register 3 undefined 0x00 5436 ri_iocmr1 i/o control mode register 1 0x00 0x00 5437 ri_iocmr3 i/o control mode register 2 0x00 0x00 5438 ri_iocmr3 i/o control mode register 3 0x00 0x00 5439 ri_iosr1 i/o switch register 1 0x00 0x00 543a ri_iosr2 i/o switch register 2 0x00 0x00 543b ri_iosr3 i/o switch register 3 0x00 0x00 543c reserved area (1 byte) 0x3f 0x00 543d ri_ascr1 analog switch register 1 0x00 0x00 543e ri_ascr2 analog switch register 2 0x00 0x00 543f ri_rcr resistor control register 1 0x00 0x00 5440 comp comp_csr1 comparator control and status register 1 0x00 0x00 5441 comp_csr2 comparator cont rol and status register 2 0x00 0x00 5442 comp_csr3 comparator cont rol and status register 3 0x00 0x00 5443 comp_csr4 comparator cont rol and status register 4 0x00 0x00 5444 comp_csr5 comparator cont rol and status register 5 0x00 table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151xx, stm8l152xx 48/101 doc id 15962 rev 2 table 8. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x03 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f cpu reserved area (85 bytes) 0x00 7f60 cfg_gcr global configuration register 0x00 0x00 7f70 itc-spr itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) stm8l151xx, stm8l152xx memory and register map doc id 15962 rev 2 49/101 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) 1. accessible by debug module only table 8. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status interrupt vector mapping stm8l151xx, stm8l152xx 50/101 doc id 15962 rev 2 6 interrupt vector mapping table 9. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address reset reset yes yes yes yes 0x00 8000 trap software interrupt - - - - 0x00 8004 1 flash eop/wr_pg_dis - - yes yes (2) 0x00 800c 2 dma1 0/1 dma1 channels 0/1 - - yes yes (2) 0x00 8010 3 dma1 2/3 dma1 channels 2/3 - - yes yes (2) 0x00 8014 4 rtc rtc alarm interrupt yes yes yes yes 0x00 8018 5 exti e/f/pvd (3) porte/f interrupt/pvd interrupt ye s ye s ye s ye s (2) 0x00 801c 6 extib external interrupt port b yes yes yes yes (2) 0x00 8020 7 extid external interrupt port d yes yes yes yes (2) 0x00 8024 8 exti0 external interrupt 0 yes yes yes yes (2) 0x00 8028 9 exti1 external interrupt 1 yes yes yes yes (2) 0x00 802c 10 exti2 external interrupt 2 yes yes yes yes (2) 0x00 8030 11 exti3 external interrupt 3 yes yes yes yes (2) 0x00 8034 12 exti4 external interrupt 4 yes yes yes yes (2) 0x00 8038 13 exti5 external interrupt 5 yes yes yes yes (2) 0x00 803c 14 exti6 external interrupt 6 yes yes yes yes (2) 0x00 8040 15 exti7 external interrupt 7 yes yes yes yes (2) 0x00 8044 16 lcd lcd interrupt - - yes yes 0x00 8048 17 clk/ tim1/ dac system clock switch/css interrupt/tim1 break/dac - - yes yes 0x00 804c 18 comp /adc1 comparator interrupt/adc1 ye s ye s ye s ye s (2) 0x00 8050 19 tim2 update /overflow/trigger/break --yesyes (2) 0x00 8054 20 tim2 capture/compare - - yes yes (2) 0x00 8058 21 tim3 update /overflow/trigger/break --yesyes (2) 0x00 805c 22 tim3 capture/compare - - yes yes (2) 0x00 8060 23 tim1 update /overflow/trigger/ com ---yes (2) 0x00 8064 24 tim1 capture/compare - - - yes (2) 0x00 8068 stm8l151xx, stm8l152xx interrupt vector mapping doc id 15962 rev 2 51/101 25 tim4 update/overflow/trigger - - yes yes (2) 0x00 806c 26 spi1 end of transfer yes yes yes yes (2) 0x00 8070 27 usart 1 transmission complete/transmit data register empty --yesyes (2) 0x00 8074 28 usart 1 receive register data full/overrun/idle line detected/parity error --yesyes (2) 0x00 8078 29 i 2 c1 i 2 c1 interrupt (4) ye s ye s ye s ye s (2) 0x00 807c 1. the low power wait mode is entered when executing a wfe instruction in low power run mode. 2. in wfe mode, this interrupt is served if it has been previ ously enabled. after processing t he interrupt, the processor goes back to wfe mode. when this interrupt is configured as a wakeup event, the cpu wakes up and resumes processing. 3. the interrupt from pvd is logically or-ed with port e and f in terrupts. register exti_conf allows to select between port e and port f interrupt (see external interrupt port sele ct register (exti_conf) in the rm0031). 4. the device is woken up from halt or active-halt mode only when the address received matches the interface address. table 9. interrupt mapping (continued) irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address option bytes stm8l151xx, stm8l152xx 52/101 doc id 15962 rev 2 7 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated memory block. all option bytes can be modified in icp mode (with swim) by accessing the eeprom address. see ta b l e 1 0 for details on option byte addresses. the option bytes can also be modified ?on the fly? by the application in iap mode, except for the rop, ubc and pcodesize values which can only be taken into account when they are modified in icp mode (with the swim). refer to the stm8l15x flash programming manual (pm0051) and stm8 swim and debug manual (um0320) for information on swim programming procedures. table 10. option byte addresses addr. option name option byte no. option bits factory default setting 7654 3 2 1 0 00 4800 read-out protection (rop) opt1 rop[7:0] 0x00 00 4802 ubc(user boot code size) opt3 ubc[7:0] 0x00 00 4807 pcodesize opt8 pcode[7:0] 0x00 00 4808 independent watchdog option opt5 [3:0] reserved wwdg _halt wwdg _hw iwdg _halt iwdg _hw 0x00 00 4809 number of stabilization clock cycles for hse and lse oscillators opt10 reserved hsecnt[1:0] lsecnt[1:0] 0x00 00 480a brownout reset (bor) opt11 [3:0] reserved bor_th bor_ on 0x01 stm8l151xx, stm8l152xx option bytes doc id 15962 rev 2 53/101 table 11. option byte description option byte no. option description opt0 rop[7:0] memory readout protection (rop) 0xaa: enable readout protection (write access via swim protocol) refer to readout protection section in the stm8l15x reference manual (rm0031). opt1 ubc[7:0] size of the user boot code area 0x00: no ubc 0x01: the ubc contains only the interrupt vectors. 0x02: page 0 and 1 reserved for the ubc and read/writ e protected. page 0 contai ns only the interrupt vectors. 0x03 - page 0 to 3 reserved for ubc, memory write-protected 0xff - page 0 to 255 reserved for ubc, memory write-protected refer to user boot code section in the stm8l15x reference manual (rm0031). opt2 pcodesize[7:0] size of the proprietary code area 0x00: no proprietary code area 0x02: page 0 and 1 reserved for the proprietary code and read/write protected. page 0 contains only the interrupt vectors. 0xff - page 0 o 254 reserved for the proprietary code. only page 1 to 254 are read/write protected. page 255 is always left free. refer to proprietary code area (pcode) section in the stm8l reference manual (rm0013) for more details. opt3 iwdg_hw: independent watchdog 0: independent watchdog activated by software 1: independent watchdog activated by hardware iwdg_halt: independent window watchdog reset on halt/active-halt 0: independent watchdog continues running in halt/active-halt mode 1: independent watchdog stopped in halt/active-halt mode wwdg_hw: window watchdog 0: window watchdog activated by software 1: window watchdog activated by hardware wwdg_halt: window window watchdog reset on halt/active-halt 0: window watchdog stopped in halt mode 1: window watchdog generates a reset when mcu enters halt mode opt4 hsecnt : number of hse oscillato r stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles lsecnt : number of lse oscillat or stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles option bytes stm8l151xx, stm8l152xx 54/101 doc id 15962 rev 2 opt5 bor_on : 0 - brownout reset off 1 - brownout reset on bor_th[3:1] : brownout reset thresholds. refer to ta b l e 1 6 for details on the thresholds according to the value of bor_th bits. table 11. option byte description (continued) option byte no. option description stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 55/101 8 electrical parameters 8.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 8.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 8.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 8.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 8.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . figure 9. pin loading conditions 50 pf stm8l pin electrical parameters stm8l151xx, stm8l152xx 56/101 doc id 15962 rev 2 8.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 10. pin input voltage 8.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in stm8l pin table 12. voltage characteristics symbol ratings min max unit v dd - v ss external supply voltage (including v dda and v ddio ) (1) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external power supply. -0.3 4.0 v v in input voltage on true open-drain pins (pc0 and pc1) v ss -0.3 v dd + 4.6 input voltage on ft pins (pa7 and pe0) v ss -0.3 v dd + 4.6 input voltage on any other pin (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in max imum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 59/101 8.3.2 power-up / power- down operating conditions table 16. operating conditions at power-up / power-down (1) symbol parameter conditions min typ max unit t vdd v dd rise time rate 0 (2) s/v v dd fall time rate 0 (2) t temp reset release delay v dd rising tbd tbd ms v pdr power-down reset threshold falling edge tbd 1.5 tbd v v bor0 brown-out reset threshold 0 (bor_th[2:0]=000) falling edge tbd 1.7 tbd rising edge tbd 1.76 tbd v bor1 brown-out reset threshold 1 (bor_th[2:0]=001) falling edge tbd 1.93 tbd rising edge tbd 2.03 tbd v bor2 brown-out reset threshold 2 (bor_th[2:0]=010) falling edge tbd 2.30 tbd rising edge tbd 2.41 tbd v bor3 brown-out reset threshold 3 (bor_th[2:0]=011) falling edge tbd 2.55 tbd rising edge tbd 2.66 tbd v bor4 brown-out reset threshold 4 (bor_th[2:0]=100) falling edge tbd 2.80 tbd rising edge tbd 2.90 tbd v pvd0 pvd threshold 0 falling edge tbd 1.85 tbd rising edge tbd 1.94 tbd v pvd1 pvd threshold 1 falling edge tbd 2.04 tbd rising edge tbd 2.14 tbd v pvd2 pvd threshold 2 falling edge tbd 2.24 tbd rising edge tbd 2.34 tbd v pvd3 pvd threshold 3 falling edge tbd 2.44 tbd rising edge tbd 2.54 tbd v pvd4 pvd threshold 4 falling edge tbd 2.64 tbd rising edge tbd 2.74 tbd v pvd5 pvd threshold 5 falling edge tbd 2.83 tbd rising edge tbd 2.94 tbd v pvd6 pvd threshold 6 falling edge tbd 3.05 tbd rising edge tbd 3.15 tbd 1. based on characterization results, unless otherwise specified. 2. guaranteed by design, not tested in production. electrical parameters stm8l151xx, stm8l152xx 60/101 doc id 15962 rev 2 figure 11. por/bor thresholds 6 vdd internal nrst 6 " / 2 " / 2 t h r e s h o l d " / 2 4 h r e s h o l d ? 0 $ 2 4 h r e s h o l d w i t h " / 2 w i t h o u t " / 2 4 i m e w i t h " / 2 3 a f e 2 e s e t 2 e s e t a t p o w e r u p " / 2 a c t i v a t e d b y u s e r f o r p o w e r d o w n d e t e c t i o n 6 d d vdd operating power supply 6 w i t h o u t " / 2 " a t t e r y l i f e e x t e n s i o n 6 0 $ 2 3 a f e 2 e s e t r e l e a s e " / 2 a l w a y s a c t i v e stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 61/101 8.3.3 supply current characteristics total current consumption the mcu is placed under the following conditions: all i/o pins in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if explicitly mentioned. subject to general operating conditions for v dd and t a . table 17. total current consumption in run mode (1) symbol parameter conditions (2) typ max unit 55c 85 c (3) 105 c (4) 125 c (4) i dd(run) supply current in run mode (5) all peripherals off, code executed from ram, v dd from 1.65 v to 3.6 v hsi rc osc. (16 mhz) f cpu = 125 khz 0.5 tbd tbd tbd tbd ma f cpu = 1 mhz 0.6 tbd tbd tbd tbd f cpu = 4 mhz 0.9 tbd tbd tbd tbd f cpu = 8 mhz 1.3 tbd tbd tbd tbd f cpu = 16 mhz 2 tbd tbd tbd tbd hse external clock (16 mhz) f cpu = 125 khz tbd tbd tbd tbd tbd f cpu = 1 mhz tbd tbd tbd tbd tbd f cpu = 4 mhz tbd tbd tbd tbd tbd f cpu = 8 mhz tbd tbd tbd tbd tbd f cpu = 16 mhz tbd tbd tbd (6) tbd tbd (6) lsi rc osc. (typ. 38 khz) f cpu = lsi tbd lse external clock (32.768 khz) f cpu = lse tbd tbd tbd (6) tbd tbd (6) electrical parameters stm8l151xx, stm8l152xx 62/101 doc id 15962 rev 2 i dd(run) supply current in run mode all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v hsi rc osc. f cpu = 125 khz tbd tbd tbd tbd tbd ma f cpu = 1 mhz 0.7 tbd tbd tbd tbd f cpu = 4 mhz 1.4 tbd tbd tbd tbd f cpu = 8 mhz 2.3 tbd tbd tbd tbd f cpu = 16 mhz tbd tbd tbd tbd tbd hse external clock (16 mhz) f cpu = 125 khz tbd tbd tbd tbd tbd f cpu = 1 mhz tbd tbd tbd tbd tbd f cpu = 4 mhz tbd tbd tbd tbd tbd f cpu = 8 mhz tbd tbd tbd tbd tbd f cpu = 16 mhz tbd tbd tbd tbd tbd lsi rc osc. f cpu = lsi tbd lse external clock (32.768 khz) f cpu = lse tbd tbd tbd tbd tbd 1. based on characterization result s, unless otherwise specified 2. all peripherals off, v dd from 1.65 v to 3.6 v, hsi internal rc osc. , f cpu =f sysclk 3. for devices with suffix 6. 4. for devices with suffix 3. 5. cpu executing typical data processing 6. data guaranteed, each individual device tested in production. table 17. total current consumption in run mode (1) (continued) symbol parameter conditions (2) typ max unit 55c 85 c (3) 105 c (4) 125 c (4) stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 63/101 table 18. total current consumption in wait mode (1) symbol parameter conditions (2) typ max unit 55c 85 c (3) 105 c (4) 125 c (4) i dd(wait) supply current in wait mode cpu not clocked, all peripherals off, code executed from ram with flash switched off, v dd from 1.65 v to 3.6 v hsi f cpu = 125 khz 430 tbd tbd tbd tbd a f cpu = 1 mhz 450 tbd tbd tbd tbd f cpu = 4 mhz 515 tbd tbd tbd tbd f cpu = 8 mhz 600 tbd tbd tbd tbd f cpu = 16 mhz 770 tbd tbd tbd tbd hse crystal oscillator (16 mhz) f cpu = 125 khz tbd tbd tbd tbd tbd f cpu = 1 mhz tbd tbd tbd tbd tbd f cpu = 4 mhz tbd tbd tbd tbd tbd f cpu = 8 mhz tbd tbd tbd tbd tbd f cpu = 16 mhz tbd tbd tbd tbd tbd lsi f cpu = lsi 32 lse crystal oscillator (32.768 khz) f cpu = lse tbd tbd tbd tbd tbd i dd(wait) supply current in wait mode cpu not clocked, all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v hsi f cpu = 125 khz 480 tbd tbd tbd tbd a f cpu = 1 mhz 500 tbd tbd tbd tbd f cpu = 4 mhz 560 tbd tbd tbd tbd f cpu = 8 mhz 660 tbd tbd tbd tbd f cpu = 16 mhz 840 tbd tbd tbd tbd hse crystal oscillator (16 mhz) f cpu = 125 khz tbd tbd tbd tbd tbd f cpu = 1 mhz tbd tbd tbd tbd tbd f cpu = 4 mhz tbd tbd tbd tbd tbd f cpu = 8 mhz tbd tbd tbd tbd tbd f cpu = 16 mhz tbd tbd tbd tbd tbd lsi f cpu = lsi 83 lse crystal oscillator (32.768 khz) f cpu = lse tbd tbd tbd tbd tbd 1. based on characterization results, unless specified 2. all peripherals off, v dd from 1.65 v to 3.6 v, hsi internal rc osc. , f cpu = f sysclk 3. for temperature range 6. 4. for temperature range 3. electrical parameters stm8l151xx, stm8l152xx 64/101 doc id 15962 rev 2 table 19. total current consumption and timing in low power run mode at v dd = 1.65 v to 3.6 v (1)(2) symbol parameter conditions typ max unit i dd(lpr) supply current in low power run mode lsi rc osc. (at 38 khz) all peripherals off t a = -40 c to 25 c 5.4 a t a = 55 c tbd t a = 85 c 6.8 t a = 105 c 9.2 t a = 125 c 13.4 with tim2 active (3) t a = -40 c to 25 c 5.7 t a = 55 c tbd t a = 85 c 7.2 t a = 105 c 9.4 t a = 125 c 13.8 lse external clock (32.768 khz) all peripherals off t a = -40 c to 25 c tbd tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd t a = 125 c tbd tbd with tim2 active (3) t a = -40 c to 25 c tbd tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd t a = 125 c tbd tbd 1. no floating i/os 2. based on characterization results, unless otherwise specified 3. timer 2 clock enabl ed and counter running stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 65/101 table 20. total current consumption in low power wait mode at v dd = 1.65 v to 3.6 v (1)(2) symbol parameter con ditions typ max unit i dd(lpw) supply current in low power wait mode lsi rc osc. (at 38 khz) all peripherals off t a = -40 c to 25 c 3 a t a = 55 c tbd t a = 85 c 4.4 t a = 105 c 6.7 t a = 125 c 11 with tim2 active (3) t a = -40 c to 25 c 3.4 t a = 55 c tbd t a = 85 c 4.8 t a = 105 c 7 t a = 125 c 11.3 lse external clock (32.768 khz) all peripherals off t a = -40 c to 25 c tbd tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd t a = 125 c tbd tbd with tim2 active (3) t a = -40 c to 25 c tbd tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd t a = 125 c tbd tbd 1. no floating i/os. 2. based on characterization results, unless otherwise specified. 3. timer 2 clock enabl ed and counter running. electrical parameters stm8l151xx, stm8l152xx 66/101 doc id 15962 rev 2 table 21. total current consumption and timing in active-halt mode at v dd = 1.65 v to 3.6 v (1)(2) symbol parameter conditions typ max unit i dd(ah) supply current in active-halt mode lsi rc (at 38 khz) lcd off t a = -40 c to 25 c tbd a t a = 55 c tbd t a = 85 c tbd t a = 105 c tbd t a = 125 c tbd lcd on (static duty) (3) t a = -40 c to 25 c tbd t a = 55 c tbd t a = 85 c tbd t a = 105 c tbd t a = 125 c tbd lcd on (1/4 duty) (4) t a = -40 c to 25 c tbd t a = 55 c tbd t a = 85 c tbd t a = 105 c tbd t a = 125 c tbd lse external clock (32.768 khz) lcd off t a = -40 c to 25 c tbd tbd a t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd t a = 125 c tbd tbd lcd on (static duty) (3) t a = -40 c to 25 c tbd tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd t a = 125 c tbd tbd lcd on (1/4 duty) (4) t a = -40 c to 25 c tbd tbd t a = 55 c tbd tbd t a = 85 c tbd tbd t a = 105 c tbd tbd t a = 125 c tbd tbd i dd(wufah) supply current during wakeup time from active-halt mode (using hsi) tbd ma stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 67/101 t wu_hsi(ah) (5)(6) wakeup time from active-halt mode to run mode (using hsi) 5tbd s t wu_lsi(ah) (5)(6) wakeup time from active-halt mode to run mode (using lsi) tbd tbd s 1. no floating i/o, unles s otherwise specified. 2. based on characterization results, unless otherwise specified. 3. lcd enabled with external vlcd, static duty, divi sion ratio = 256, all pixels active, no lcd connected. 4. lcd enabled with external vlcd, 1/4 duty, 1/3 bias, di vision ratio = 64, all pixels active, no lcd connected. 5. wakeup time until start of interrupt vector fetch. the first word of interrupt routi ne is fetched 4 cpu cycles after t wu . 6. ulp=0 or ulp=1 and fwu=1 in the pwr_csr2 register. table 21. total current consumption and timing in active-halt mode at v dd = 1.65 v to 3.6 v (1)(2) (continued) symbol parameter conditions typ max unit table 22. total current consumption and timing in halt mode at v dd = 2 v (1)(2) symbol parameter condition typ max unit i dd(halt) supply current in halt mode (ultra low power ulp bit =1 in the pwr_csr2 register ) t a = -40 c to 25 c 400 tbd na t a = 55 c tbd tbd (3) t a = 85 c tbd tbd t a = 105 c tbd tbd (3) i dd(wuhalt) supply current during wakeup time from halt mode (using hsi) tbd ma t wu_hsi(halt) (4)(5) wakeup time from halt to run mode (using hsi) 5tbds t wu_lsi(halt) (4)(5) wakeup time from halt mode to run mode (using lsi) tbd tbd s 1. t a = -40 to 125 c, no floating i/o, unless otherwise specified 2. based on characterization results, unless otherwise specified 3. tested in production 4. ulp=0 or ulp=1 and fwu=1 in the pwr_csr2 register 5. wakeup time until start of interrupt vector fetch. the first word of interrupt routi ne is fetched 4 cpu cycles after t wu electrical parameters stm8l151xx, stm8l152xx 68/101 doc id 15962 rev 2 current consumption of on-chip peripherals table 23. peripheral current consumption symbol parameter typ. v dd = 3.0 v unit i dd(tim1) tim1 supply current (1) 13 a/mhz i dd(tim2) tim2 supply current (1) 8 i dd(tim3) tim3 supply current (1) 8 i dd(tim4) tim4 timer supply current (1) 3 i dd(usart1) usart1 supply current (2) 6 i dd(spi1) spi1 supply current (2) 3 i dd(i2c1) i 2 c1 supply current (2) 5 i dd(dma1) dma1 supply current 3 i dd(wwdg) wwdg supply current 2 i dd(all) peripherals on (3) 44 a/mhz i dd(rtc) rtc supply current when clocked by lsi tbd a rtc supply current when clocked at 1 mhz tbd i dd(lcd) lcd supply current when clocked at 32 khz /2 tbd lcd supply current when clocked at 1 mhz /2 tbd i dd(adc1) adc1 supply current (4) 1500 a i dd(dac) dac supply current (5) 370 i dd(comp1) comparator 1 supply current (6) 0.160 i dd(comp2) comparator 2 supply current (6) slow mode 2 fast mode 5 i dd(pvd/bor) power voltage detector and brownout reset unit supply current (7) 2.8 i dd(idwdg) independent watchdog supply current tbd 1. data based on a differential i dd measurement between all peripherals off an d a timer counter running at 16 mhz. the cpu is in wait mode in both cases. no ic/oc progr ammed, no i/o pins toggling. not tested in production. 2. data based on a differential i dd measurement between the on-chip peripheral in reset configuration and not clocked and the on-chip peripheral when clocked and not kept under reset. the cpu is in wait mode in both cases. no i/o pins toggling. not tested in production. 3. peripherals listed above the i dd(all) parameter on: tim1, tim2, tim3, tim4, usart1, spi1, i2c1, dma1, wwdg. 4. data based on a differential i dd measurement between adc in reset conf iguration and continuous adc conversion. 5. data based on a differential i dd measurement between dac in reset confi guration and continuous dac conversion of v dd /2. dac output is in high-impedance. 6. data based on a differential i dd measurement between comp1 or comp2 in reset configuration and comp1 or comp2 enabled with static inputs. supply current of internal reference voltage excluded. 7. including supply current of internal reference voltage. stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 69/101 8.3.4 clock and timi ng characteristics hse external clock (hsebyp = 1 in clk_eckcr) subject to general operating conditions for v dd and t a . lse external clock (lsebyp=1 in clk_eckcr) subject to general operating conditions for v dd and t a . table 24. hse external clock characteristics symbol parameter conditions min typ max unit f hse_ext external clock source frequency (1) 1. guarenteed by design, not tested in production. 116mhz v hseh (2) 2. data based on characterization results, not tested in production. osc_in input pin high level voltage 0.7 x v dd tbd v v hsel (2) osc_in input pin low level voltage v ss 0.3 x v dd c in(hse) osc_in input capacitance (1) tbd pf i leak_hse osc_in input leakage current v ss < v in < v dd tbd tbd na table 25. lse external clock characteristics symbol parameter min typ max unit f lse_ext external clock source frequency (1) 1 32.768 tbd khz v lseh (2) osc32_in input pin high level voltage 0.7 x v dd tbd v v lsel (2) osc32_in input pin low level voltage v ss 0.3 x v dd c in(hse) osc32_in input capacitance (1) tbd pf i leak_hse osc32_in input leakage current tbd tbd na 1. guarenteed by design, not tested in production. 2. data based on characterization results, not tested in production. electrical parameters stm8l151xx, stm8l152xx 70/101 doc id 15962 rev 2 hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and startup stabilization time. refer to the crys tal resonator manufactur er for more details (frequency, package, accuracy...). figure 12. hse oscillator circuit diagram hse oscillator critical g m formula r m : notional resistance (see crystal specification), l m : notional inductance (see crystal specification), c m : notional capacitance (see crystal specification), co: shunt capacitance (see crystal specification), c l1 =c l2 =c: grounded external capacitance g m >> g mcrit table 26. hse oscillator characteristics symbol parameter conditions min typ max unit f hse high speed external oscillator frequency 116mhz r f feedback resistor tbd k c (1) recommended load capacitance (2) tbd pf i dd(hse) hse oscillator power consumption c = 20 pf, f osc = 16 mhz tbd (startup) tbd (stabilized) (3) ma c = 10 pf, f osc =16 mhz tbd (startup) tbd (stabilized) (3) g m oscillator transconductance 3.5 ma/v t su(hse) (4) startup time v dd is stabilized 1 ms 1. c= c l1 = c l2 is approximately equival ent to 2 x crystal cload. 2. the oscillator selection can be optimized in terms of supply current using a high qual ity resonator with small r m value. refer to crystal manufacturer for more details 3. data based on characterization results, not tested in production. 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabili zed 16 mhz oscillation. this value is measured for a standar d crystal resonator and it can vary signi ficantly with the crystal manufacturer. osc_out osc_in f hse to core c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator g mcrit 2 f hse () 2 r m 2co c + () 2 = stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 71/101 lse crystal/ceramic resonator oscillator the lse clock can be supplied with a 32.768 kh z crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and startup stabilization time. refer to the crys tal resonator manufactur er for more details (frequency, package, accuracy...). figure 13. lse oscillator circuit diagram table 27. lse oscillator characteristics symbol parameter conditions min typ max unit f lse low speed external oscillator frequency 32.768 khz r f feedback resistor tbd k c (1) recommended load capacitance (2) tbd pf i dd(lse) lse oscillator power consumption tbd (3) a g m oscillator transconductance tbd a/v t su(lse) (4) startup time v dd is stabilized ms 1. c= c l1 = c l2 is approximately equiva lent to 2 x crystal c load . 2. the oscillator selection can be optimized in terms of s upply current using a high qualit y resonator with a small r m value. refer to crystal manufacturer for more details 3. data based on characterization results, not tested in production. 4. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabi lized 32.768 khz oscillation. this value is measured for a standard crys tal resonator and it can vary signific antly with the crystal manufacturer. osc_out osc_in f lse c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator electrical parameters stm8l151xx, stm8l152xx 72/101 doc id 15962 rev 2 internal clock sources subject to general operating conditions for v dd , and t a . high speed internal rc oscillator (hsi) low speed internal rc oscillator (lsi) table 28. hsi oscillator characteristics (1) symbol parameter conditions min typ max unit f hsi frequency v dd = 3.0 v 16 mhz acc hsi accuracy of hsi oscillator (factory calibrated) v dd = 3.0 v, t a = 25 c -1 (2) 1 (2) % v dd = 3.0 v, 0 c t a 55 c -1.5 (2) 1.5 (2) % v dd = 3.0 v, -10 c t a 70 c -2 (2) 2 (2) % v dd = 3.0 v, -10 c t a 85 c -2.5 (2) 2 (2) % v dd = 3.0 v, -10 c t a 125 c -4.5 (2) 2 (2) % 1.65 v v dd 3.6 v, -40 c t a 125 c -4.5 3 % trim hsi user trim resolution 1.65 v v dd 3.6 v, -40 c t a 125 c 0.4 (2) 0.5 % t su(hsi) hsi oscillator setup time (wakeup time) 3.7 7.4 (2) s i dd(hsi) hsi oscillator power consumption 100 140 (2) a 1. v dd = 3.0 v, t a = -40 to 125 c unless otherwise specified. 2. data based on characterization results, not tested in production. table 29. lsi oscillator characteristics (1) 1. v dd = 1.8 v to 3.0 v, t a = -40 to 125 c unless otherwise specified. symbol parameter conditions min typ max unit f lsi frequency 26 38 56 khz t su(lsi) lsi oscillator wakeup time tbd tbd (2) 2. data based on characterization results, not tested in production. s i dd(lsi) lsi oscillator frequency drift (3) 3. this is a deviation for an individual part, once the in itial frequency has been measured. 0 c t a 85 c -10 4 % stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 73/101 8.3.5 memory characteristics t a = -40 to 125 c unless otherwise specified. table 30. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by characterization, not tested in production. flash memory halt mode (or reset) 1.4 v table 31. flash program memory symbol parameter conditions min typ max (1) unit v dd operating voltage (all modes, read/write/erase) f sysclk = 16 mhz 1.65 3.6 v t prog programming time for 1 or 128 bytes (block) erase/write cycles (on programmed byte) tbd ms programming time for 1 to 128 bytes (block) write cycles (on erased byte) tbd ms i prog programming/ erasing consumption t a = +25 c, v dd = 3.0 v tbd ma t a = +25 c, v dd = 1.8 v tbd t ret data retention (program memory) after 10000 erase/write cycles at t a = +85 c t ret = +55 c tbd (1) years data retention (data memory) after 10000 erase/write cycles at t a = +85 c t ret = +55 c tbd (1) data retention (data memory) after 10000 erase/write cycles at t a = +85 c t ret = +85 c tbd (1) n rw erase/write cycles (program memory) see notes (1)(2) tbd (1) kcycles erase/write cycles (data memory) see notes (1)(3) tbd (1) (4) 1. data based on characterization results, not tested in production. 2. retention guaranteed after cycling is 10 years @ 55 c. 3. retention guaranteed after cycling is 1 year @ 55 c. 4. data based on characterization performed on the whole data memory. electrical parameters stm8l151xx, stm8l152xx 74/101 doc id 15962 rev 2 8.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 32. i/o static characteristics (1) symbol parameter conditions min typ max unit v il input low level voltage (2) input voltage on true open-drain pins (pc0 and pc1) v ss -0.3 0.3 x v dd v input voltage on ft pins (pa7 and pe0) v ss -0.3 0.3 x v dd input voltage on any other pin v ss -0.3 0.3 x v dd v ih input high level voltage (2) input voltage on true open-drain pins (pc0 and pc1) 0.70 x v dd v dd +3.6 v input voltage on ft pins (pa7 and pe0) 0.70 x v dd v dd +3.6 input voltage on any other pin 0.70 x v dd v ddmax +0.3 v hys schmitt trigger voltage hysteresis (3) standard i/os 200 mv true open drain i/os 250 i lkg input leakage current (4) v ss v in v dd standard i/os --50 (5) na v ss v in v dd true open drain i/os - - 200 (5) v ss v in v dd pa0 with high sink led driver capability - - 200 (5) r pu weak pull-up equivalent resistor (6) v in = v ss 30 45 60 k c io (7) i/o pin capacitance 5 pf 1. v dd = 3.0 v, t a = -40 to 125 c unless otherwise specified. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switchin g levels. based on characterization results, not tested. 4. the max. value may be exceeded if negative current is injected on adjacent pins. 5. not tested in production. 6. r pu pull-up equivalent resistor based on a resistive transistor. 7. data guaranteed by design, not tested in production. stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 75/101 output driving current subject to general operating conditions for v dd and t a unless otherwise specified. table 33. output driving current (standard ports) i/o type symbol parameter conditions min max unit standard v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 13 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +2 ma, v dd = 3.0 v 0.45 v i io = +2 ma, v dd = 1.8 v 0.45 v i io = +10 ma, v dd = 3.0 v 0.7 v v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in table 13 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin i io = -2 ma, v dd = 3.0 v v dd -0.45 v i io = -1 ma, v dd = 1.8 v v dd -0.45 v i io = -10 ma, v dd = 3.0 v v dd -0.7 v table 34. output driving current (true open drain ports) i/o type symbol parameter conditions min max unit open drain v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 13 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +3 ma, v dd = 3.0 v 0.45 i io = +1 ma, v dd = 1.8 v 0.45 table 35. output driving current (pa0 wi th high sink led driver capability) i/o type symbol parameter conditions min max unit ir v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 13 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +20 ma, v dd = 2.0 v tbd electrical parameters stm8l151xx, stm8l152xx 76/101 doc id 15962 rev 2 nrst pin subject to general operating conditions for v dd and t a unless otherwise specified. the reset network shown in figure 14 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il max. level specified in ta bl e 3 6 . otherwise the reset is not taken into account internally. figure 14. recommended nrst pin configuration table 36. nrst pin characteristics symbol parameter conditions min typ (1) max unit v il(nrst) nrst input low level voltage (1) 1. data based on characterization results, not tested in production. v ss 0.8 v v ih(nrst) nrst input high level voltage (1) 1.4 v dd v ol(nrst) nrst output low level voltage i ol = 2 ma v dd -0.8 r pu(nrst) nrst pull-up equivalent resistor (2) 2. the r pu pull-up equivalent resistor is based on a resistive transistor 30 45 60 k v f(nrst) nrst input filtered pulse (3) 3. data guaranteed by design, not tested in production. 50 ns v nf(nrst) nrst input not filtered pulse (3) 300 0.01 f external reset circuit stm8l filter r pu v dd internal reset rstin stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 77/101 8.3.7 communication interfaces spi1 - serial peripheral interface unless otherwise specified, the parameters given in ta bl e 3 7 are derived from tests performed under ambient temperature, f sysclk frequency and v dd supply voltage conditions summarized in section 8.3.1 . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 37. spi1 characteristics symbol parameter conditions (1) 1. parameters are given by se lecting 10 mhz i/o output frequency. min max unit f sck 1/t c(sck) spi clock frequency master mode 0 8 mhz slave mode 0 8 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf - tbd ns t su(nss) (2) 2. values based on design simulation and/or charac terization results, and not tested in production. nss setup time slave mode 4 x 1/f sysclk - t h(nss) (2) nss hold time slave mode tbd - t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f sysclk = 8 mhz, f sck = 4 mhz tbd tbd t su(mi) (2) t su(si) (2) data input setup time master mode tbd - slave mode tbd - t h(mi) (2) t h(si) (2) data input hold time master mode tbd - slave mode tbd - t a(so) (2)(3) 3. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode - 3x 1/f sysclk t dis(so) (2)(4) 4. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. data output disable time slave mode tbd - t v(so) (2) data output valid time slave mode (after enable edge) - tbd t v(mo) (2) data output valid time master mode (after enable edge) -tbd t h(so) (2) data output hold time slave mode (after enable edge) tbd - t h(mo) (2) master mode (after enable edge) tbd - electrical parameters stm8l151xx, stm8l152xx 78/101 doc id 15962 rev 2 figure 15. spi timing diagram - slave mode and cpha=0 figure 16. spi timing diagram - slave mode and cpha=1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 79/101 figure 17. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) electrical parameters stm8l151xx, stm8l152xx 80/101 doc id 15962 rev 2 i 2 c - inter ic control interface subject to general operating conditions for v dd , f sysclk , and t a unless otherwise specified. the stm8l i 2 c interface (i2c1) meets the requirements of the standard i 2 c communication protocol described in the following table with the restriction mentioned below: refer to i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl). note: for speeds around 200 khz, the achieved speed can have a 5% tolerance for other speed ranges, the achieved speed can have a 2% tolerance the above variations depend on the accuracy of the external components used. table 38. i2c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f sysclk must be at least equal to 8 mhz to achieve max fast i 2 c speed (400 khz). unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production. max (2) min (2) max (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 0 900 t r(sda) t r(scl) sda and scl rise time 1000 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 81/101 figure 18. typical application with i 2 c bus and timing diagram 1) 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd 8.3.8 lcd control ler (stm8l152xx only) repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda scl 4.7k sda stm8l scl v dd 100 100 v dd 4.7k i 2 cbus table 39. lcd characteristics (1) 1. data guaranteed by design, not tested in production. symbol parameter min typ max. unit v lcd lcd external voltage 3.6 v v lcd0 lcd internal reference voltage 0 2.6 v v lcd1 lcd internal reference voltage 1 2.7 v v lcd2 lcd internal reference voltage 2 2.8 v v lcd3 lcd internal reference voltage 3 2.9 v v lcd4 lcd internal reference voltage 4 3.0 v v lcd5 lcd internal reference voltage 5 3.1 v v lcd6 lcd internal reference voltage 6 3.2 v v lcd7 lcd internal reference voltage 7 3.3 v cext v lcd external capacitance 0.1 2 f i dd supply current (2) at v dd = 1.8 v 2. lcd enabled with 3 v internal booster (lcd_cr1 = 0x08), 1/ 4 duty, 1/3 bias, division ratio= 64, all pixels active, no lcd connected. tbd supply current (2) at v dd = 3 v tbd r h low drive resistive network tbd m r l high drive resistive network tbd k v 33 segment/common higher level voltage v lcdx v v 23 segment/common 2/3 level voltage 2/3v lcdx v v 12 segment/common 1/2 level voltage 1/2v lcdx v v 13 segment/common 1/3 level voltage 1/3v lcdx v v 0 segment/common lowest level voltage 0 v electrical parameters stm8l151xx, stm8l152xx 82/101 doc id 15962 rev 2 vlcd external capacitor (stm8l152xx only) the application can achieve a stabilized lcd reference voltag e by connecting an external capacitor c ext to the v lcd pin. c ext is specified in ta bl e 3 9 . 8.3.9 embedded reference voltage 8.3.10 temperature sensor table 40. reference voltage characteristics (1) symbol parameter min typ max. unit i refint internal reference voltage consumption 1.4 a t s_vrefint adc sampling time when reading the internal reference voltage (2) 510 s i buf internal reference voltage buffer consumption (used for adc) 13.5 25 a v refint out reference voltage output tbd 1.225 tbd v v refint_div1 1/4 reference voltage 25 %v refint_comp v refnt_div2 1/2 reference voltage 50 v refnt_div3 3/4 reference voltage 75 i lpbuf internal reference voltage low power buffer consumption (used for comparators or output) 730 1200 na i refout buffer ouptut current (3) 1a c refout reference voltage output load 50 pf t vrefint internal reference voltage startup time 2 tbd ms t bufen internal reference voltage buffer startup time once enabled (2) 10 s acc vrefint accuracy of v refint stored in engibyte 5 mv stab vrefint stability of v refint in temperature 20 50 ppm/c stab vrefint stability of v refint after 1000 hours tbd ppm 1. based on characterization result s, unless otherwise specified 2. defined when adc output reaches its final value 1/2lsb 3. to guaranty less than 1% v refout deviation table 41. ts characteristics (1) symbol parameter min typ max. unit v 25 sensor reference voltage at 25c tbd 0.495 tbd v t l v sensor linearity with temperature tbd tbd c avg_slope average slope tbd tbd tbd mv/c idd (temp) consumption 3.4 6 a stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 83/101 8.3.11 comparator characteristics t start temperature sensor startup time (2) 10 s t s_temp adc sampling time when reading the temperature sensor 510s 1. based on characterization results, unless otherwise specified. 2. defined for adc output reaches its final value 1/2lsb. table 41. ts characteristics (1) (continued) symbol parameter min typ max. unit table 42. comparator 1 characteristics symbol parameter min (1) 1. data guaranteed by design, not tested in production. typ max (1) unit v dda analog supply voltage 1.65 3.6 v t a temperature range -40 125 c r 400 r 400 value tbd 400 tbd k err 400 error on r 400 tbd % r 10 r 10 value tbd 10 tbd k err 10 error on r 10 tbd % v in comparator input voltage range 0 v dda v v refint internal reference reference voltage tbd 1.225 tbd t start startup time after enable 7 tbd s t d propagation delay (2) 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 3tbds v offset comparator offset error tbd 3 tbd mv i cmp1 consumption (3) 3. comparator consumption only. inte rnal reference voltage not included. 160 tbd na table 43. comparator 2 characteristics symbol parameter conditions min (1) typ max (1) unit v dda analog supply voltage 1.65 3.6 v t a temperature range -40 125 c v in comparator input voltage range 0 v dda v t start startup time after enable in fast mode 1.65 v to 2.7 v tbd s 2.7 v to 3.6 v tbd startup time after enable in slow mode 1.65 v to 2.7 v tbd s 2.7 v to 3.6 v tbd electrical parameters stm8l151xx, stm8l152xx 84/101 doc id 15962 rev 2 8.3.12 12-bit dac characteristics t df propagation delay in fast mode (2) 1.65 v to 2.7 v tbd tbd s 2.7 v to 3.6 v tbd tbd t ds propagation delay in slow mode (2) 1.65 v to 2.7 v tbd tbd s 2.7 v to 3.6 v tbd tbd v offset comparator offset error 1.65 v to 2.7 v tbd tbd mv 2.7 v to 3.6 v tbd tbd i dd(cmp2f) consumption in fast mode 1.65 v to 2.7 v tbd tbd a 2.7 v to 3.6 v tbd tbd i dd(cmp2s) consumption in slow mode 1.65 v to 2.7 v tbd tbd a 2.7 v to 3.6 v tbd tbd 1. data guaranteed by design, not tested in production. 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. table 43. comparator 2 characteristics symbol parameter conditions min (1) typ max (1) unit table 44. dac characteristics, output on pf0 (1) symbol parameter conditions min (2) typ max (1) unit v dda analog supply voltage 1.8 3.6 v v ref+ reference supply voltage 1.8 3.6 v t a temperature range -40 125 c i vdda current on v dda supply no load, middle code 0x800 on the inputs 370 tbd a no load, worst code 0xf1c @ v ref+ =3.6v on the inputs 500 tbd i vref+ current on v ref+ supply 210 tbd r l resistive load (3) dacout buffer on 5 k r o output impedance dacout buffer off tbd k c l capacitive load (4) 50 pf dac_out dac_out voltage (5) dacout buffer on 0.2 v ref+ -0.2 v dacout buffer off 0 v ref+ v dnl differential non linearity (6) r l 5k , c l 50 pf dacout buffer on 1 tbd 12-bit lsb c l 50 pf dacout buffer off -tbdtbd stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 85/101 inl integral non linearity (7) r l 5k , c l 50 pf dacout buffer on 2 tbd 12-bit lsb c l 50 pf dacout buffer off tbd tbd offset offset error (8) r l 5k , c l 50 pf dacout buffer on 20 tbd mv c l 50 pf dacout buffer off tbd tbd gain error gain error r l 5k , c l 50 pf dacout buffer on 0.5 tbd % c l 50 pf dacout buffer off tbd tbd tue total unadjusted error r l 5k , c l 50 pf dacout buffer on tbd tbd 12-bit lsb c l 50 pf dacout buffer off tbd tbd t settling settling time (full scale: for a 12- bit input code transition between the lowest and the highest input codes when dac_out reaches the final value 1lsb r l 5k , c l 50 pf 7tbds update rate max frequency for a correct dac_out (@95%) change when small variation of the input code (from code i to i+1lsb). r l 5k , c l 50 pf 1 msps t wakeup wakeup time from off state. input code between lowest and highest possible codes. r l 5k , c l 50 pf 9tbds psrr+ power supply rejection ratio (to v dda ) (static dc measurement ) r l 5k , c l 50 pf -60 -35 db 1. for 48-pin package only. 2. data guaranteed by design, not tested in production. 3. resistive load between dacout and gnda. 4. capacitive load at dacout pin. 5. it gives the output excursion of the dac. 6. difference between two consecutive codes - 1 lsb. 7. difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023. 8. difference between measured value and ideal value=v ref /2. table 44. dac characteristics, output on pf0 (1) (continued) symbol parameter conditions min (2) typ max (1) unit electrical parameters stm8l151xx, stm8l152xx 86/101 doc id 15962 rev 2 table 45. dac output on pb4-pb5-pb6 (1) 1. 32 or 28-pin packages only. the da c channel can be routed either on pb4 , pb5 or pb6 using the routing interface i/o switch registers. symbol parameter min (2) 2. data guaranteed by design, not tested in production. typ max (1) unit r int internal resistance between dac output and pb4-pb5-pb6 output tbd tbd k stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 87/101 8.3.13 12-bit adc1 characteristics table 46. adc1 characteristics symbol parameter conditions min (1) 1. data guaranteed by design, not tested in production. typ max (1) unit v dda analog supply voltage 1.8 3.6 v v ref+ reference supply voltage 2.4 v v dda 3.6 v 2.4 v dda v 1.8 v v dda 2.4 v v dda v v ref- lower reference voltage v ssa v i vdda current on the v dda input pin 1000 a i vref+ current on the v ref+ input pin 400 tbd a v ain conversion voltage range 0 (2) 2. v ref- or v dda must be tied to ground. v ref+ t a temperature range -40 125 c r ain external resistance on v ain tbd (3) 3. for 1 msps, maximum rext is 0.5 k . k r adc sampling switch resistance on pf0 fast channel tbd k on all other channels tbd k c adc internal sample and hold capacitor on pf0 fast channel tbd pf on all other channels tbd pf f adc adc sampling clock frequency 2.4 v v dda 3.6 v without zooming 0.320 16 mhz 1.8 v v dda 2.4 v with zooming 0.320 8 mhz f s sampling rate v ain on pf0 fast channel 0.02 1 (4) 4. value obtained for continous conversion on fast channel. mhz v ain on all other channels f trig external trigger frequency tbd 1/f adc t lat external trigger latency tbd 1/f adc t s sampling time v ain on fast channel pf0 4 (4) 1/f adc v ain on slow channels tbd 1/f adc t conv conversion time 12 + t s 1/f adc 16 mhz 1 (3) s t wkup wakeup time from off state 3 s t vrefint internal reference voltage startup time refer to ta b l e 4 0 ms electrical parameters stm8l151xx, stm8l152xx 88/101 doc id 15962 rev 2 general pcb design guidelines power supply decoupling should be performed as shown in figure 19 or figure 20 , depending on whether v ref+ is connected to v dda or not. good quality ceramic 10 nf capacitors should be used. they should be placed as close as possible to the chip. figure 19. power supply and reference decoupling (v ref+ not connected to v dda ) table 47. adc1 accuracy symbol parameter typ max (1) unit dnl differential non linearity tbd 1 lsb inl integral non linearity tbd 2 lsb tue total unadjusted error tbd 5 lsb offset offset error tbd 2 lsb gain gain error tbd 3.5 lsb enob effective number of bits tbd 9.5 bits sinad signal-to-noise and distortion ratio tbd tbd db snr signal-to-noise ratio tbd tbd db thd total harmonic distorsion tbd tbd db 1. data based on characterization, not tested in production. v ref+ stm8l v dda v ssa /v ref- 1 f // 10 nf 1 f // 10 nf ai17031 stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 89/101 figure 20. power supply and reference decoupling (v ref+ connected to v dda ) 8.3.14 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. functional ems (electromagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 61000 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). v ref+ /v dda stm8l 1 f // 10 nf v ref? /v ssa ai17032 electrical parameters stm8l151xx, stm8l152xx 90/101 doc id 15962 rev 2 electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm iec61967-2 which specifies the board and the loading of each pin. absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and charge device model. this test conforms to the jesd22-a114a/a115a standard. table 48. ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f cpu = 16 mhz, conforms to iec 61000 tbd v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f cpu = 16 mhz, conforms to iec 61000 tbd table 49. emi data (1) 1. not tested in production. symbol parameter conditions monitored frequency band max vs. unit 16 mhz s emi peak level v dd = 3.6 v, t a = +25 c, lqfp32 conforming to iec61967-2 0.1 mhz to 30 mhz tbd db v 30 mhz to 130 mhz tbd 130 mhz to 1 ghz tbd sae emi level 1 - stm8l151xx, stm8l152xx electrical parameters doc id 15962 rev 2 91/101 static latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. 8.4 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 15: general operating conditions on page 58 . the maximum chip-junction temperature, t jmax , in degree celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: t amax is the maximum ambient temperature in c ja is the package junction-to-ambient thermal resistance in c/w p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh )*i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. table 50. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) 1000 table 51. electrical sensitivities symbol parameter class lu static latch-up class ii electrical parameters stm8l151xx, stm8l152xx 92/101 doc id 15962 rev 2 table 52. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient wfqfpn28 - 4 x 4 mm tbd c/w ja thermal resistance junction-ambient lqfp 32 - 7 x 7 mm tbd c/w ja thermal resistance junction-ambient vfqfpn 32 - 5 x 5 mm tbd c/w ja thermal resistance junction-ambient lqfp 48- 7 x 7 mm tbd c/w ja thermal resistance junction-ambient vfqfpn 48- 7 x 7mm tbd c/w stm8l151xx, stm8l152xx package characteristics doc id 15962 rev 2 93/101 9 package characteristics 9.1 ecopack in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark. package characteristics stm8l151xx, stm8l152xx 94/101 doc id 15962 rev 2 9.2 package mechanical data figure 21. wfqfpn28 ? 28-lead very very thin fine pitch quad flat no-lead package outline (4x4) (1) figure 22. recommended footprint (dimensions in mm) (1) 1. drawing is not to scale. dg_me b 15 21 22 2 8 1 7 d e b e e ddd ddd l1 14 l2 a1 a a3 table 53. wfqfpn28 ? 28-lead very very thin fine pitch quad flat no-lead package (4 x 4), package mechanical data (1) dim. mm inches (2) min typ max min typ max a (1) 0.7 0.75 0.8 0.0276 0.0295 0.0315 a1 0 0.02 0.05 0 0.0008 0.002 a3 0.2 0.0079 b 0.18 0.25 0.3 0.0071 0.0098 0.0118 d 4 0.1575 e 4 0.1575 e 0.5 0.0197 l1 0.25 0.35 0.45 0.0098 0.0138 0.0177 l2 0.3 0.4 0.5 0.0118 0.0157 0.0197 ddd 0.08 0.0031 number of pins n28 1. thickness valid for the wfqfpn28 package in the sampli ng phase. in the production phase, the ufqfpn28 package will be used with a thickness equal to 0.6 mm. 2. values in inches are converted from mm and rounded to 4 decimal digits. stm8l151xx, stm8l152xx package characteristics doc id 15962 rev 2 95/101 figure 23. wfqfpn32 ? 32-lead very very th in fine pitch quad flat no-lead package outline (5 x 5) 1. the exposed pad must be soldered to the pcb. it is recommended to connect it to v ss . seating plane ddd c c a3 a1 a d e 9 16 17 24 32 pin # 1 id r = 0.30 8 e l l d2 1 b e2 a0a3_me bottom view table 54. wfqfpn32 ? 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data (1) dim. mm inches (2) min typ max min typ max a (1) 0.70 0.75 0.80 0.0276 0.0295 0.0315 a1 0 0.02 0.05 0.0008 0.0020 a3 0.20 0.0079 b 0.18 0.25 0.30 0.0071 0.0098 0.0118 d 4.85 5.00 5.15 0.1909 0.1969 0.2028 d2 3.20 3.45 3.70 0.1260 0.1358 0.1457 e 4.85 5.00 5.15 0.1909 0.1969 0.2028 e2 3.20 3.45 3.70 0.1260 0.1358 0.1457 e 0.50 0.0197 l 0.30 0.40 0.50 0.0118 0.0157 0.0197 ddd 0.08 0.0031 number of pins n32 1. thickness valid for the wfqfpn32 package in the sampli ng phase. in the production phas e, the ufqfpn32 package will be used with a thickness equal to 0.6 mm. 2. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm8l151xx, stm8l152xx 96/101 doc id 15962 rev 2 figure 24. lqfp32 ? 32-pin low profile quad flat package outline 5v_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 16 17 24 25 b 32 1 pin 1 identification 8 9 table 55. lqfp32 ? 32-pin low profile quad flat package, package mechanical data dim. mm inches (1) min typ max min typ max a1.60.063 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.3 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.2 0.0035 0.0079 d 8.8 9 9.2 0.3465 0.3543 0.3622 d1 6.8 7 7.2 0.2677 0.2756 0.2835 d3 5.6 0.2205 e 8.8 9 9.2 0.3465 0.3543 0.3622 e1 6.8 7 7.2 0.2677 0.2756 0.2835 e3 5.6 0.2205 e 0.8 0.0315 l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 1 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.1 0.0039 number of pins n32 1. values in inches are converted from mm and rounded to 4 decimal digits. stm8l151xx, stm8l152xx package characteristics doc id 15962 rev 2 97/101 figure 25. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package outline (1)(2) figure 26. recommended footprint (dimensions in mm) (1) 1. drawing is not to scale. 2. the exposed pad must be soldered to the pcb. it is recommended to connect it to v ss . seating plane a3 a1 a2 a d e e e2 b e l l d2 b v0_me c 12 13 24 25 36 37 1 48 7.30 7.30 0.20 0.30 0.55 0.50 5.80 6.20 6.20 5.60 5.60 5.80 0.75 ai15697 48 1 12 13 24 25 36 37 table 56. vfqfpn48 ? very thin fine pitch quad flat pack no-lead 7 7 mm, 0.5 mm pitch package mechanical data (1) symbol millimeters inches (2) typ min max typ min max a (1) 0.900 0.800 1.000 0.0354 0.0315 0.0394 a1 0.020 0.050 0.0008 0.0020 a2 0.650 1.000 0.0256 0.0394 a3 0.250 0.0098 b 0.230 0.180 0.300 0.0091 0.0071 0.0118 d 7.000 6.850 7.150 0.2756 0.2697 0.2815 d2 4.700 2.250 5.250 0.1850 0.0886 0.2067 e 7.000 6.850 7.150 0.2756 0.2697 0.2815 e2 4.700 2.250 5.250 0.1850 0.0886 0.2067 e 0.500 0.450 0.550 0.0197 0.0177 0.0217 l 0.400 0.300 0.500 0.0157 0.0118 0.0197 ddd 0.080 0.0031 1. thickness valid for the vfqfpn48 package in the sampli ng phase. in the production phase, the ufqfpn48 package will be used with a thickness equal to 0.6 mm. 2. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm8l151xx, stm8l152xx 98/101 doc id 15962 rev 2 figure 27. lqfp48 ? 48-pin low profile quad flat package outline (7x7) 5b_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13 table 57. lqfp48 ? 48-pin low profile quad flat package (7x7), package mechanical data dim. mm inches (1) min typ max min typ max a1.60.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.2 0.0035 0.0079 d 8.8 9 9.2 0.3465 0.3543 0.3622 d1 6.8 7 7.2 0.2677 0.2756 0.2835 d3 5.5 0.2165 e 8.8 9 9.2 0.3465 0.3543 0.3622 e1 6.8 7 7.2 0.2677 0.2756 0.2835 e3 5.5 0.2165 e 0.5 0.0197 l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 1 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.08 0.0031 number of pins n48 1. values in inches are converted from mm and rounded to 4 decimal digits. stm8l151xx, stm8l152xx device ordering information doc id 15962 rev 2 99/101 10 device ordering information figure 28. stm8l15xxx ordering information scheme stm8 l 151 c 4 u 6 product class stm8 microcontroller pin count c = 48 pins k = 32 pins g = 28 pins package u = wfqfpn or vfqfpn t = lqfp example: sub-family type 151 = ultralow power 152 = ultralow power with lcd family type l = low power temperature range 3 = - 40 c to 125 c 6 = - 40 c to 85 c for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the st sales office nearest to you. program memory size 4 = 16 kbytes 6 = 32 kbytes revision history stm8l151xx, stm8l152xx 100/101 doc id 15962 rev 2 11 revision history table 58. document revision history date revision changes 06-aug-2009 1 initial release 10-sep-2009 2 updated peripheral naming throughout document. added figure 6: stm8l151cx 48-pin pinout (without lcd) on page 24 added capacitive sensing channels in features on page 1 updated pa7, pc0 and pc1 in table 4: stm8l15x pin description changed clk and remap register names in ta bl e 7 changed description of wdghalt in ta b l e 1 1 added typical power consumption values in ta b l e 1 6 to ta bl e 2 3 correct vih max in ta bl e 3 2 stm8l151xx, stm8l152xx doc id 15962 rev 2 101/101 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their 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